Data Sheet

AD4020/AD4021/AD4022

Rev. B | Page 31 of 39

CS MODE, 3-WIRE WITHOUT THE BUSY INDICATOR

This mode is typically used when a single AD4020/AD4021/

AD4022 device is connected to an SPI-compatible digital host.

The connection diagram is shown in Figure 55, and the

corresponding timing diagram is shown in Figure 56.

Turbo mode must be disabled to use this mode. To disable turbo

mode, set the turbo mode enable bit in the configuration register

to 0 (see Table 12). Turbo mode is disabled by default.

When performing conversions in this mode, SDI must be held

high. SDI can be connected to VIO if register reading and writing is

not required. A rising edge on CNV initiates a conversion and

forces SDO to high impedance. After a conversion is initiated, it

continues until completion, irrespective of the state of CNV. This

feature can be useful when bringing CNV low to select other

SPI devices, such as analog multiplexers. However, CNV must

elapses and then held high for the maximum possible

conversion time to avoid generating the busy signal indicator.

When the conversion is complete, the AD4020/AD4021/AD4022

enter the acquisition phase and power down. There must not be

any digital activity on SCK during the conversion.

When CNV goes low, the MSB is output onto SDO. The

remaining data bits are clocked out on SDO by subsequent SCK

falling edges. The data is valid on both SCK edges. Although the

rising edge can capture the data, a digital host using the SCK

falling edge allows a faster reading rate, provided it has an

status bits are not enabled, SDO returns to high impedance after

edges (see the Status Bits section). SDO returns to high

impedance after the final SCK falling edge, or when CNV goes

high (whichever occurs first).

AD4020/

AD4021/

AD4022

SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

VIO

TO WRITE TO THE CONFIGURATION REGISTER.

Figure 55. CS Mode, 3-Wire Without Busy Indicator Connection Diagram

SDO

D19

D18

D17

D1

D0

SCK

12

3

18

19

20

HSDO

CNV

CONVERSION

ACQUISITION

ACQUISITION

SDI = 1

Figure 56. CS Mode, 3-Wire Without the Busy Indicator Serial Interface Timing Diagram (Status Bits Not Shown)