AD4021BCPZ-R2 datasheet(21/39 Pages) AD

21 / 39 page

Data Sheet

AD4020/AD4021/AD4022

Rev. B | Page 21 of 39

10µF

REF

VDD

VIO

GND

IN+

IN–

SDI

SCK

SDO

CNV

AD4020/

AD4021/

AD4022

3-WIRE/4-WIRE

INTERFACE

1.8V

1.8V TO 5V

DIGITAL HOST

(MICROPROCESSOR/

FPGA)

4.096V

0.1µF

VOCM

1kΩ

+IN

V+

–IN

–OUT

+OUT

1kΩ

10kΩ

1kΩ

DIFFERENTIAL

AMPLIFIER

1kΩ

0.1µF

VREF/2

HOST

SUPPLY

V–

REF

V+ = +5V

LDO

AMP

VREF

VREF/2

VREF

VREF/2

0.1µF

VREF/2

Figure 42. Typical Application Diagram with a Fully Differential Amplifier

ANALOG INPUTS

Figure 43 shows an equivalent circuit of the analog input

structure, including the overvoltage clamp of the

AD4020/AD4021/AD4022.

CEXT

REXT

VIN

REF

IN+/IN–

GND

CLAMP

0V TO 15V

RIN

CIN

CPIN

Figure 43. Equivalent Analog Input Circuit

Input Overvoltage Clamp Circuit

Most ADC analog inputs, IN+ and IN−, have no overvoltage

protection circuitry apart from ESD protection diodes. During

an overvoltage event, an ESD protection diode from an analog

input pin (IN+ or IN−) to REF forward biases and shorts the

input pin to REF, potentially overloading the reference or

damaging the device. The AD4020/AD4021/AD4022 internal

overvoltage clamp circuit with a larger external resistor (REXT =

200 Ω) eliminates the need for external protection diodes and

protects the ADC inputs against dc overvoltages.

In applications where the amplifier rails are greater than VREF

and less than ground, it is possible for the output to exceed the

input voltage range (specified in Table 1) of the device. In this

case, the AD4020/AD4021/AD4022 internal voltage clamp

circuit ensures that the voltage on the input pin does not exceed

VREF + 0.4 V and prevents damage to the device by clamping the

input voltage in a safe operating range and avoiding disturbance of

the reference, which is particularly important for systems that

share the reference among multiple ADCs.

If the analog input exceeds the reference voltage by 0.4 V, the

internal clamp circuit turns on and the current flows through

the clamp into ground, preventing the input from rising further

and potentially causing damage to the device. The clamp turns

on before D1 (see Figure 43) and can sink up to 50 mA of current.

When the clamp is active, it sets the overvoltage (OV) clamp

flag bit in the configuration register that is accessed with a

16-bit SPI read command or via the OV in the status bits. The

OV clamp flag gives an indication of overvoltage condition

when it is set to 0. The OV clamp flag is a read only sticky bit,

and is cleared only if the register is read while the overvoltage

condition is no longer present.

The clamp circuit does not dissipate static power in the off state.

Note that the clamp cannot sustain the overvoltage condition

for an indefinite amount of time.

The external RC filter, formed by Resistor REXT and Capacitor CEXT

(see Figure 43), is usually present at the ADC input to band limit

the input signal. During an overvoltage event, excessive voltage

is dropped across REXT, and REXT becomes part of a protection

circuit. The REXT value can vary from 200 Ω to 20 kΩ for 15 V

protection. The CEXT value can be as low as 100 pF for correct

operation of the clamp. See Table 1 for input overvoltage clamp

specifications.

Differential Input Considerations

The analog input structure allows the sampling of the true

differential signal between IN+ and IN−. By using these differential

inputs, signals common to both inputs are rejected. Figure 32

shows the common-mode rejection capability of the AD4020/

AD4021/AD4022 over frequency. It is important to note that the

differential input signals must be truly antiphase in nature, 180° out

of phase, which is required to keep the common-mode voltage of

the input signal within the specified range around VREF/2, as

shown in Table 1.

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