Data Sheet

AD4020/AD4021/AD4022

Rev. B | Page 35 of 39

CS MODE, 4-WIRE WITH THE BUSY INDICATOR

This mode is typically used when a single AD4020/AD4021/

AD4022 device is connected to an SPI-compatible digital host

with an interrupt input (IRQ), and when CNV, which samples

the analog input, is required to be independent of the signal

used to select the data reading. This independence is particularly

important in applications where low jitter on CNV is desired.

The connection diagram is shown in Figure 63, and the

corresponding timing is shown in Figure 64.

Turbo mode must be disabled to use this mode. To disable turbo

mode, set the turbo mode enable bit in the configuration

register to 0 (see Table 12). Turbo mode is disabled by default.

A rising edge on CNV initiates a conversion and forces SDO to

high impedance. When performing conversions in this mode,

SDI must be high during the CNV rising edge. CNV must be

held high throughout the conversion and data readback phase.

When performing conversions in this mode, SDI must be high

during the CNV rising edge. Prior to the minimum conversion

multiplexers. However, SDI must be returned low before the

minimum conversion time elapses and then held low for the

maximum possible conversion time to guarantee generating the

busy signal indicator. When the conversion is complete, the

AD4020/AD4021/AD4022 enter the acquisition phase and

power down. There must not be any digital activity on SCK

during the conversion.

When the conversion is complete, SDO is driven low. With a

pull-up resistor (for example, 1 kΩ) on the SDO line, this

transition can be used as an interrupt signal to initiate the data

reading controlled by the digital host. The data bits are then

clocked out MSB first on SDO by subsequent SCK falling edges.

The data is valid on both SCK edges. Although the rising edge

can capture the data, a digital host using the SCK falling edge

allows a faster reading rate, provided it has an acceptable hold

clocked out on SDO on the first 20 SCK falling edges. If the

SDO returns to high impedance after an optional additional

SCK falling edge or the next CNV rising edge (whichever

occurs first).

SDI

SDO

CNV

SCK

CS1

CONVERT

DATA IN

CLK

DIGITAL HOST

IRQ

VIO

1kΩ

AD4020/

AD4021/

AD4022

Figure

SDO

D0

D1

D18

D19

SCK

12

3

19

20

21

CONVERSION

ACQUISITION

ACQUISITION

SDI

CNV

Figure 64. CS Mode, 4-Wire with the Busy Indicator Serial Interface Timing Diagram (Status Bits Not Shown)