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AD4021BCPZ-R2 数据表(PDF) 28 Page - Analog Devices

部件名 AD4021BCPZ-R2
功能描述  20-Bit, 1.8 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs
PDF  39 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD4021BCPZ-R2 数据表(HTML) 28 Page - Analog Devices

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AD4020/AD4021/AD4022
Data Sheet
Rev. B | Page 28 of 39
tCYC
tSCK
tSCKL
tSCKH
tSCNVSCK
tSSDISCK
tHSDISCK
tCNVH1
tEN
tHSDO
tDSDO
tDIS
tHCNVSCK
tQUIET22
1THE CNV HIGH TIME MUST FOLLOW THE tCONV SPECIFICATION TO GENERATE A VALID CONVERSION RESULT.
2THE SCK FALLING EDGE TO CNV RISING EDGE DELAY MUST FOLLOW THE tQUIET2 SPECIFICATION TO ENSURE SPECIFIED PERFORMANCE.
SDO
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
CONVERSION RESULT ON D19 TO D0
SDI
0
1
0
1
R/W
WEN
B0
B1
B2
B3
B4
B5
B6
B7
0
0
1
1
(0)
(0)
8-BIT REGISTER ACCESS COMMAND
REGISTER DATA ON B7 TO B0
SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CNV
Figure 50. Register Write Timing Diagram
SDIA
SDOA/SDIB
SDOB
0
0
COMMAND (0x14)
0
0
COMMAND (0x14)
0
0
COMMAND (0x14)
tCYC
tSCK
tSCKL
tSCKH
tSCNVSCK
CNV
SCK
1
24
tDIS
tCNVH
DATA (0xAB)
DATA (0xAB)
Figure 51. Register Write Timing Diagram, Daisy-Chain Mode



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