AD4021BCPZ-R2 datasheet(36/39 Pages) AD

36 / 39 page

AD4020/AD4021/AD4022

Data Sheet

Rev. B | Page 36 of 39

DAISY-CHAIN MODE

Use this mode to daisy-chain multiple AD4020/AD4021/AD4022

devices on a 3-wire or 4-wire serial interface. This feature is useful

for reducing component count and wiring connections such as

cases with isolated multiconverter applications or for systems

with a limited interfacing capacity. Data readback is analogous

to clocking a shift register. A connection diagram example using

two AD4020/AD4021/AD4022 devices is shown in Figure 65,

and the corresponding timing diagram is shown in Figure 66.

Turbo mode must be disabled to use this mode. To disable turbo

mode, set the turbo mode enable bit in the configuration

disabled by default.

When SDI and CNV are low, SDO is driven low. A rising edge

on CNV initiates a conversion and SDO remains low. When

performing conversions in this mode, SDI and SCK must be

low during the CNV rising edge. CNV must be held high

throughout the conversion and data readback phase.

When the conversion is complete, the MSB is output onto SDO

of each device, and the AD4020/AD4021/AD4022 enter the

acquisition phase and power down. The remaining data bits are

clocked out on SDO by subsequent SCK falling edges. For each

ADC, SDI feeds the input of the internal shift register and is

clocked in on each SCK rising edge. Results are therefore passed

through each device until they are all received by the digital

host. When the status bits are disabled, 20 × N clocks are required

to read back N ADCs. When the status bits are enabled, 26 × N

clocks are required to read back the conversion data and status

bits for N ADCs. The data is valid on both SCK edges.

The maximum achievable conversion rate when using daisy-chain

mode is typically less than when reading a single device because

the number of bits to clock out is larger (see the Serial Clock

Frequency Requirements section).

It is possible to write to each ADC register in daisy-chain mode.

The timing diagram is shown in Figure 51. This mode requires

4-wire operation because data is clocked in on the SDI line with

CNV held low. The same command byte and register data can

be shifted through the entire chain to program all ADCs in the

chain with the same register contents, which requires 8 × (N + 1)

clocks for N ADCs. It is possible to write different register contents

to each ADC in the chain by first writing to the furthest ADC in

the chain first, using 8 × (N + 1) clocks, and then the second

furthest ADC with 8 × N clocks, and so forth until reaching the

nearest ADC in the chain, which requires 16 clocks for the

command and register data. It is not possible to read register

contents in daisy-chain mode.

CONVERT

DATA IN

CLK

DIGITAL HOST

DEVICE B

DEVICE A

AD4020/

AD4021/

AD4022

AD4020/

AD4021/

AD4022

SDI1

SDO

CNV

SCK

SDI

SDO

CNV

SCK

1SDI MUST BE CONNECTED TO THE DIGITAL HOST DATA OUT TO WRITE TO THE CONFIGURATION REGISTER.

Figure 65. Daisy-Chain Mode, Connection Diagram

DA19

DA18

DA17

SCK

tSSDISCK

tHSDISCK

CONVERSION

ACQUISITION

tCONV

tCYC

tACQ

ACQUISITION

CNV

DA1

tSCK

tSCKL

tSCKH

DA0

SDIA = 0

SDOB

DB19

DB18

DB17

DA1

DB1DB0DA19

DA18

tHSDO

tDSDO

tQUIET2

tHSCKCNV

DA0

tDIS

tQUIET2

tEN

SDOA = SDIB

Figure 66. Daisy-Chain Mode Serial Interface Timing Diagram (Status Bits Not Shown)

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