MPC8275VR datasheet(41/76 Pages) MOTOROLA

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MOTOROLA

MPC8280 PowerQUICC II™ Family Hardware Speciﬁcations

Pinout

This section provides the pin assignments and pinout lists for both HiP7 PowerQUICC II packages.

8.1

ZU Package—MPC8280 and MPC8270

The following ﬁgures and table represent the standard 480 TBGA package. For information on the alternate

package, refer to Section 8.2, “VR and ZQ Packages—MPC8275 and MPC8270” on page 56.

Figure 13 shows the pinout of the ZU package as viewed from the top surface.

1 “Low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency guarantees

the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock mode.

For modes with a CPU multiplication factor

≤ 3, the minimum CPU frequency is 166 MHz.The minimum CPM frequency

is 133 MHz.

For modes with a CPU multiplication factor

≥ 3.5, the minimum CPU frequency is 250 MHz. The minimum CPM

frequency is as shown in the table.

“High” values are for the purpose of illustration only. Users must select a mode and input bus frequency so that the

resulting conﬁguration does not exceed the frequency rating of the user’s device.

2 As shown in Table 14, PCI_MODCK determines the PCI clock range. Refer to Table 18 for higher range conﬁgurations.

3 MODCK_H = hard reset conﬁguration word [28–31]. MODCK[1-3] = three hardware conﬁguration pins.

4 CPM multiplication factor = CPM clock/PCI clock

5 CPU multiplication factor = Core PLL multiplication factor

MPC8275VR 数据表(PDF) 41 Page - Motorola, Inc