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MPC8275VR 数据表(PDF) 24 Page - Motorola, Inc |
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MPC8275VR 数据表(HTML) 24 Page - Motorola, Inc |
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24 / 76 page ![]() 24 MPC8280 PowerQUICC II™ Family Hardware Specifications MOTOROLA Clock Configuration Modes In each clocking mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven bits during the power-up reset—three hardware configuration pins (MODCK[1–3]) and four bits from hardware configuration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to the selected MPC8280 clock operation mode as described in the following sections. 7.1 Local Bus Mode Table 15 lists clock configurations for the MPC8280 in local bus mode. The frequencies listed are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device. NOTE Clock configurations change only after PORESET is asserted. Table 15. Clock Configurations for Local Bus Mode1 Mode2 Bus Clock3 (MHz) CPM Multiplication Factor4 CPM Clock (MHz) CPU Multiplication Factor5 CPU Clock (MHz) MODCK_H-MODCK[1-3] low high low high low high Default Modes (MODCK_H= 0000) 0000_000 62.5 133.3 3 187.5 400.0 4 250.0 533.3 0000_001 50.0 133.3 3 150.0 400.0 5 250.0 666.7 0000_010 62.5 100.0 4 250.0 400.0 4 250.0 400.0 0000_011 50.0 100.0 4 200.0 400.0 5 250.0 500.0 0000_100 66.7 167.0 2 133.3 334.0 2.5 166.7 417.5 0000_101 66.7 167.0 2 133.3 334.0 3 200.0 501.0 0000_110 66.7 160.0 2.5 166.7 400.0 2.5 166.7 400.0 0000_111 55.5 160.0 2.5 138.7 400.0 3 166.7 480.0 Full Configuration Modes 0001_000 66.7 167.0 2 133.3 334.0 4 266.7 668.0 0001_001 66.7 167.0 2 133.3 334.0 5 333.3 835.0 0001_010 66.7 167.0 2 133.3 334.0 6 396.0 1002.0 0001_011 Reserved 0001_100 Reserved 0001_101 62.5 133.3 3 187.5 400.0 4 250.0 533.3 0001_110 50.0 133.3 3 150.0 400.0 5 250.0 666.7 1000_111 45.5 133.3 3 136.4 400.0 5.5 250.0 733.3 0001_111 44.3 133.3 3 133.3 400.0 6 266.7 800.0 0010_000 Reserved 0010_001 Reserved |
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