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MPC8275VR 数据表(PDF) 8 Page - Motorola, Inc

部件名 MPC8275VR
功能描述  PowerQUICC II Family Hardware Specifications
PDF  76 Pages
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制造商  MOTOROLA [Motorola, Inc]
网页  http://www.freescale.com
标志 MOTOROLA - Motorola, Inc

MPC8275VR 数据表(HTML) 8 Page - Motorola, Inc

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MPC8280 PowerQUICC II™ Family Hardware Specifications
MOTOROLA
DC Electrical Characteristics
NOTE: Core, PLL, and I/O Supply Voltages
After power up sequence is complete, VDDH and VDD/VCCSYN must
track each other and both voltages must vary in the same direction. When
varying in the positive direction, VDDH may vary up to 5% from nominal
or 3.3 + 0.165 = 3.465 V, in which case VDD/VCCSYN must also vary
upward by 5% from nominal or 1.525 + 0.075 = 1.6 V. The same applies
to the negative direction: VDDH may vary downward up to -5% from
nominal or 3.3 –0.165 = 3.135 V, in which case VDD/VCCSYN must vary
downward by-5% from nominal or 1.525 –0.075 = 1.45 V. A/C timing
specification violation may occur during the time that voltage tracking is
not correct.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (either GND or VCC).
Figure 2 shows the undershoot and overshoot voltage of the 60x and local bus memory interface of the
MPC8280. Note that in PCI mode the I/O interface is different.
Figure 2. Overshoot/Undershoot Voltage
3
DC Electrical Characteristics
Table 5 shows DC electrical characteristics.
2 Note that for extended temperature parts the range is (-40)
TA
– 105Tj.
Table 5. DC Electrical Characteristics1
Characteristic
Symbol
Min
Max
Unit
Input high voltage—
all inputs except TRST and PORESET2
VIH
2.0
3.465
V
Input low voltage
VIL
GND
0.8
V
CLKIN input high voltage
VIHC
2.4
3.465
V
CLKIN input low voltage
VILC
GND
0.4
V
Input leakage current, VIN = VDDH
3
IIN
—10
µA
GND
GND – 0.3 V
GND – 1.0 V
Not to exceed 10%
GVDD
of tSDRAM_CLK
GVDD + 5%
4 V
VIH
VIL



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