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MCP3564-E/ST 数据表(PDF) 27 Page - Microchip Technology |
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MCP3564-E/ST 数据表(HTML) 27 Page - Microchip Technology |
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27 / 108 page  2019-2021 Microchip Technology Inc. DS20006181C-page 27 MCP3561/2/4 4.0 TERMINOLOGY AND FORMULAS This section defines the terms and formulas used throughout this document. The following terms are defined: • MCLK – Master Clock • AMCLK – Analog Master Clock • DMCLK – Digital Master Clock • DRCLK – Data Rate Clock • OSR – Oversampling Ratio • Offset Error • Gain Error • Integral Nonlinearity Error (INL) • Signal-to-Noise Ratio (SNR) • Signal-to-Noise and Distortion Ratio (SINAD) • Total Harmonic Distortion (THD) • Spurious-Free Dynamic Range (SFDR) • MCP3561/2/4 Delta-Sigma Architecture • Power Supply Rejection Ratio (PSRR) • Common-Mode Rejection Ratio (CMRR) • Digital Pins Output Current Consumption FIGURE 4-1: System Clock Details. 4.1 MCLK – Master Clock This is the master clock frequency at the MCLK input pin when an external clock source is selected or internal clock frequency when the internal clock is selected. 4.2 AMCLK – Analog Master Clock This is the clock frequency that is present on the analog portion of the device after prescaling has occurred via the PRE[1:0] bits. EQUATION 4-1: ANALOG MASTER CLOCK 4.3 DMCLK – Digital Master Clock This is the clock frequency that is present on the digital portion of the device. This is also the sampling frequency or the rate at which the modulator outputs are refreshed. Each period of this clock corresponds to one sample and one modulator output. See Equation 4-2. EQUATION 4-2: DIGITAL MASTER CLOCK 4.4 DRCLK – Data Rate Clock This is the output data rate in Continuous mode or the rate at which the ADC outputs new data. Any new data are signaled by a data ready pulse on the IRQ pin. This data rate depends on the OSR and the prescaler as shown in Equation 4-3. EQUATION 4-3: DATA RATE Since this is the output data rate, and since the decimation filter is a sinc (or notch) filter, there is a notch in the filter transfer function at each integer multiple of this rate. MCLK Pad 1/OSR Internal Oscillator MCLK Multiplexer OUT 1 0 1/ PRESCALE 1/4 AMCLK DMCLK DRCLK Clock Divider Clock Divider Clock Divider OSR[3:0] PRE[1:0] CLK_SEL[1] AMCLKOUT CLK_SEL[1] = 0 CLK_SEL[1:0] = 11 AMCLK MCLK Prescale ----------------------- = DMCLK AMCLK 4 --------------------- MCLK 4Prescale -------------------------------- == DRCLK DMCLK OSR ---------------------- AMCLK 4OSR --------------------- MCLK 4 OSR Prescale --------------------------------------------------- == = |
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