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MCP3564-E/ST 数据表(PDF) 65 Page - Microchip Technology

部件名 MCP3564-E/ST
功能描述  Two/Four/Eight-Channel, 153.6 ksps, Low-Noise 24-Bit Delta-Sigma ADCs
PDF  108 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

MCP3564-E/ST 数据表(HTML) 65 Page - Microchip Technology

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 2019-2021 Microchip Technology Inc.
DS20006181C-page 65
MCP3561/2/4
6.4
Reading from the Device
When the Command bit, CMD[0], is equal to ‘1’, the
command is a read communication. After the STATUS
byte has been transferred, the first register to be read
on the SDO pin is the one with the address defined by
the Command Address bits (CMD[5:2]).
Any CS rising edge during a read communication
aborts the current reading.
The registers may need 4, 8, 16, 24 or 32 bits to be fully
read depending on their address (see Table 8-1).
If the CMD[1:0] bits are equal to ‘11’, the command
type is Incremental Read. In this case, after each
register is read, the Address Pointer is automatically
incremented as long as CS stays logic low. The
following data bytes are read from the next address
sequentially defined in the register map. When the
Address Pointer reaches 0xF (last register in the regis-
ter map for reading), the next register to read is register
0x0 (see Figure 6-6 for a graphical representation of
the address looping).
FIGURE 6-6:
Incremental Read Loop.
If the CMD[1:0] bits are equal to ‘01’, the command
type is Static Read. In this case, the register address
defined in the COMMAND byte is read continuously.
The Address Pointer is automatically incremented.
Continuously clocking SCK while CS stays logic low
will continuously read the same register. Reading
another register is only possible by aborting the current
communication sequence by raising CS and issuing
another command.
In both Static and Incremental modes, the registers
are updated after each register read is fully performed.
If the value of the register changes internally during
the read, it will only be updated after the end of the
read. The value of each register is latched in the SDO
Output Shift register at the first rising edge of SCK of
each individual register reading. Figure 6-7 shows the
bit by bit details of a single register Read
communication. Figure 6-8 shows the examples of
Static and Incremental Read communications.
CONFIG0 (0x1)
CONFIG1 (0x2)
CONFIG2 (0x3)
CONFIG3 (0x4)
IRQ (0x5)
MUX (0x6)
SCAN (0x7)
TIMER (0x8)
OF FSETCAL (0x9)
GAINCAL (0xA)
Reserved (0xB)
Reserved (0xC)
LOCK (0xD)
Reserved (0xE)
CRCREG (0xF)
ADCDATA (0x0)



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