MCP3564-ESLASHST datasheet(75/108 Pages) MICROCHIP

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DS20006181C-page 75

MCP3561/2/4

6.8.3.3

IRQ Pin State

A Logic Low state is generated on the IRQ pin as soon

as the AVDD or DVDD monitoring circuits detect a power

supply drop below their specified threshold.

This POR interrupt can only be cleared when both

AVDD and DVDD are above their monitoring voltage

thresholds. When this condition is met, the POR

threshold is cleared by the CS falling edge. Therefore,

it means that if a CS falling edge does not clear the IRQ

pin state, the POR event is still in effect.

This feature helps the user to know exactly when the

chip has powered up by polling with the CS pin and

checking the IRQ pin state at power-up (see

Figure 6-15 for more details).

Since this is a high-level priority interrupt, the POR

interrupt can happen at all times, even when MDAT is

enabled. In this case, having a constant logic low bit-

stream can indicate a probable POR event (or a fully

negative ADC saturation output code induced by a

large negative input voltage).

FIGURE 6-15:

POR IRQ Timing Diagram.

6.8.4

CRCCFG ERROR INTERRUPT

The CRCCFG interrupt happens when an error in the

CRC-16 checksum has been detected in the register

map CRC calculation.

This interrupt is implemented with three different and

independent mechanisms: STATUS byte on SDO, IRQ

6.8.4.1

STATUS Byte on SDO

In case of a CRCCFG error on the next STATUS byte

transmitted on SDO, the CRCCFG_STATUS bit is logic

low. Once the STATUS byte has been transmitted, the

CRCCFG_STATUS bit appears as ‘1’ until a new inter-

rupt occurs. If the error is detected again between two

STATUS byte transmissions, the CRCCFG_STATUS

bit on SDO will appear as equal to ‘0’ on the second

reading.

6.8.4.2

IRQ Register Status Bit

In case of a CRCCFG error, the CRCCFG_STATUS bit

in the IRQ register is set to ‘0’. Once the IRQ register is

fully read, the CRCCFG_STATUS bit is reset to ‘1’. If

the CRCCFG error happens again between two read-

ings of the IRQ register, the IRQ register Status bit will

appear as ‘0’ on the second reading.

6.8.4.3

IRQ Pin State

The CRCCFG error generates a Logic Low state on the

IRQ pin until it is cleared. The clearing of the CRCCFG

error can only be made by “unlocking” the device (write

0xA5 in the LOCK[7:0] register) or by sending a Fast

command start/restart ADC conversion. Unlocking the

device stops the CRC calculation, and therefore, clears

the associated interrupt. Sending an ADC start/restart

conversion Fast command resets the CRC calculation

and clears the interrupt.

This CRCCFG error can only occur in case of an

external perturbation (for example, EMI induced) that

causes the continuous calculation of the CRC on the

integrity has been altered. Since both causes are

high-priority issues, the CRCCFG error has priority

over all other interrupts (except POR) and over the

MDAT output on the IRQ pin.

IRQ

High-Z

DVDD

AVDD

tPOR

VPOR_A, VPOR_D

Clears POR interrupt

Chip Select

Starts Low

POR

Internal State

Don’t Care

tCSIRQ

Note:

If MCLK starts running before the device is

locked, an interrupt can momentarily occur,

even if registers have not been corrupted. In

such a case, the user must send a

start/restart conversion Fast command

which will clear the unwanted interrupt and

correctly restart the CRC calculations.

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