MCP3564-ESLASHST datasheet(38/108 Pages) MICROCHIP

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MCP3561/2/4

DS20006181C-page 38

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5.5

Digital Decimation Filter

The decimation filter decimates the output bit stream of

the modulator to produce 24-bit ADC output data. The

decimation filter present in the device is a cascade of

two filters: a third-order sinc filter with a decimation

ratio of OSR3 (third-order moving an average of

3x OSR3 values), followed by a first-order sinc filter

with a decimation ratio of OSR1, moving an average of

OSR values (third-order moving average of 3 x OSR3

values).

Figure 5-4 represents the decimation filter architecture.

FIGURE 5-4:

Decimation Filter Block

Diagram.

The following equation is the transfer function of the

decimation filter:

EQUATION 5-3:

FILTER TRANSFER

FUNCTION

The resolution (number of possible output codes

expressed in powers of two or in bits) of the digital

filter is 24-bit maximum for any OSR = OSR3 x OSR1

and data format choice. The resolution only depends

on the OSR through the OSR[3:0] settings in the

CONFIG1 register per Table 5-6. Once the OSR is

chosen, the resolution is fixed and the output code of

the ADC is encoded with the data format defined by

the DATA_FORMAT[1:0] setting in the CONFIG3

The transfer function of this filter has a unity gain at

each multiple of DMCLK. A proper anti-aliasing filter

must be placed at the ADC inputs. This will attenuate

the frequency contents around each multiple of

DMCLK and keep the desired accuracy over the base-

band of the converter. This anti-aliasing filter can be a

simple first-order RC network with low time constant to

provide a high rejection at DMCLK frequency.

The conversion time is a function of the OSR settings

and the DMCLK frequency.

EQUATION 5-4:

CONVERSION TIME FOR

OSR = OSR3 x OSR1

In One-Shot mode, each conversion is launched

individually, so the maximum data rate is effectively

1/TCONV if each conversion is launched with no delay.

The digital filter is reset in between each conversion.

However, due to the nature of the digital filter (which

memorizes the sum of the incoming bit stream), the

data rate at the filter output can be maximized if the

filter is never reset. Because of the internal resampling

of the digital filter, the output data rate can be equal to

DMCLK/OSR = DRCLK; this is the case in Continuous

mode. In this case, the first conversion still happens in

the TCONV time, as this is the settling time of the filter.

The subsequent conversions are pipelined and give

their output at a data rate of DRCLK. The Continuous

Conversion mode can optimize the data rate, while

consuming the same power as One-Shot mode, which

is advantageous in applications that require a continu-

ous sampling of the analog inputs. The Continuous

mode is not compatible with multiplexing the inputs

(see Section 5.14 “SCAN Mode” for more details

about the Conversion mode settings in MUX and SCAN

modes).

Figure 5-5 shows the fundamental difference between

One-Shot mode and Continuous mode in a simplified

diagram.

Modulator

Output

(Thermometer

Coding)

SINC

Decimation

Filter

Output

OSR3

OSR1

ADC

Resolution

Decimation Filter

OSR1 = 1



-OSR3

–





OSR3 1z 1

–



3

--------------------------------------------

-OSR1 OSR3



–





OSR

OSR3

–







------------------------------------------------------



Where:

fj

DMCLK

----------------------





exp

TCONV

3OSR3





OSR1 1

–

 OSR



 DMCLK



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