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MCP3564-E/ST 数据表(PDF) 50 Page - Microchip Technology

部件名 MCP3564-E/ST
功能描述  Two/Four/Eight-Channel, 153.6 ksps, Low-Noise 24-Bit Delta-Sigma ADCs
PDF  108 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

MCP3564-E/ST 数据表(HTML) 50 Page - Microchip Technology

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MCP3561/2/4
DS20006181C-page 50
 2019-2021 Microchip Technology Inc.
FIGURE 5-11:
ADC Output and IRQ Behavior with Digital Offset Calibration Enabled.
5.12.2
DIGITAL GAIN ERROR
CALIBRATION
The Gain Error Calibration register (GAINCAL,
address: 0xA) is an unsigned 24-bit register that holds
the digital gain error calibration value, GAINCAL.
Equation 5-8 calculates the GAINCAL multiplier.
EQUATION 5-8:
GAINCAL CALIBRATION
VALUE (MULTIPLIER
VALUE)
For the MCP3561/2/4 devices, the gain error
calibration is done by multiplying the GAINCAL value
to the ADC output code.
The gain error calibration value range in equivalent
voltage is [0; 2-2-23], which can cancel any possible
gain error in the ADC and in the system. The gain
error calibration is made with a simple 24-bit
add-and-shift circuit clocked on DMCLK and induces a
pipeline delay of TGCAL = 23 DMCLK periods. This
pipeline delay acts as a delay on the data ready
interrupt position that is shifted by TGCAL = 23 DMCLK
periods.
During this delay, the converter can process the next
conversion, the delay does not shift the next
conversion and does not change the Conversion Time,
TCONV. Enabling the gain error calibration will affect
the next conversion result; the conversion result
already held in the ADCDATA register (0x0) is not
modified when the EN_GAINCAL is set to ‘1’, but the
next one will take the offset calibration into account.
Changing the GAINCAL register to a new value will
not affect the current ADCDATA value, but the next
one (after a data ready interrupt) will take the new
GAINCAL value into account. Figure 5-12 shows the
different cases and their associated effects on the
ADCDATA register and the IRQ output.
FIGURE 5-12:
ADC Output and IRQ Behavior with Digital Gain Error Calibration Enabled.
ADC DATA
REGISTER
VALUE
SPI
Wri te
EN _OFFC AL = 1
IRQ
ADC
STATUS
Data 2 Conversion
Data 1 Conversion
Data 3 Conversion
DATA1
DATA0
DATA2 + OFFSETCAL1
Wri te
OFFSE TCA L[2 3:0] = OFFSE TCA L1
Wri te
OFFSE TCA L[2 3:0] = OFFSE TCA L2
Data 4 Conversion
DATA3 + OFFSETCAL2
GAINCAL (V/V) = (GAINCAL[23:0] unsigned decimal
code)/8388608
SPI
Wri te
EN _GAINCAL = 1
IRQ
ADC
STATUS
Data 3 Conversion
DATA1
DATA0
DATA2 x GAINCAL1
Wri te
GAIN C AL[2 3:0] = GAIN C AL1
Wri te
GAIN C AL[2 3:0] = GAIN C AL2
Data 4 Conversion
DATA3 x GAINCAL2
TGCAL
TGCAL
ADCDATA
Data 2 Conversion
Data 1 Conversion



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