ADP5065ACBZ-1-R7 datasheet(32/40 Pages) AD

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ADP5065

Data Sheet

Rev. D | Page 32 of 40

APPLICATIONS INFORMATION

EXTERNAL COMPONENTS

Inductor Selection

The high switching frequency of the ADP5065 buck converter

allows for the selection of small chip inductors. Suggested

inductors are shown in Table 33.

The peak-to-peak inductor current ripple is calculated using

the following equation:

OUT

RIPPLE

−

)

(

where:

VOUT is the ISO_Sx node output voltage.

VIN is the converter input voltage at the CFILT node.

fSW is the switching frequency.

L is the inductor value.

The minimum dc current rating of the inductor must be greater

than the inductor peak current. The inductor peak current is

calculated using the following equation:

)

(

RIPPLE

MAX

LOAD

CHG

PEAK

Inductor conduction losses are caused by the flow of current

through the inductor, which has an associated internal dc

resistance (DCR). Larger sized inductors have smaller DCR,

which may decrease inductor conduction losses. Inductor core

losses are related to the magnetic permeability of the core material.

Because the bucks are high switching frequency dc-to-dc

converters, shielded ferrite core material is recommended for

its low core losses and low EMI.

ISO_Sx (VOUT) and ISO_Bx Capacitor Selection

To safely obtain stable operation of the ADP5065, the ISO_Sx

and ISO_Bx effective capacitance (including temperature and

dc bias effects) must not be less than 10 µF at any point during

operation. The combined effective capacitance of the ISO_Sx

capacitor and the system capacitance must not exceed 50 µF at

any point during operation.

Higher output capacitor values reduce the output voltage ripple

and improve load transient response. When choosing this value,

it is also important to account for the loss of capacitance due to

output voltage dc bias.

Ceramic capacitors are manufactured with a variety of dielec-

trics, each with a different behavior over temperature and

applied voltage. Capacitors must have a dielectric adequate

enough to ensure the minimum capacitance over the necessary

temperature range and dc bias conditions. X5R or X7R dielectrics

with a voltage rating of 6.3 V or 10 V are recommended for best

performance. Y5V and Z5U dielectrics are not recommended

for use with any dc-to-dc converter because of their poor temper-

ature and dc bias characteristics.

The worst-case capacitance accounting for capacitor variation

over temperature, component tolerance, and voltage is calcu-

lated using the following equation:

CEFF = COUT × (1 − TEMPCO) × (1 − TOL)

where:

CEFF is the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient

(TEMPCO) over −40°C to +85°C is assumed to be 15% for an

X5R dielectric. The tolerance of the capacitor (TOL) is assumed

to be 10%, and COUT is 16 μF at 4.2 V, as shown in Figure 39.

Substituting these values in the equation yields

CEFF = 16 μF × (1 − 0.15) × (1 − 0.1) ≈ 12.24 μF

DC BIAS (V)

Figure 39. Murata GRM31CR60J226ME19C DC Characteristic

To guarantee the performance of the charger in various

operation modes including trickle charge, constant current

charge, and constant voltage charge, it is imperative that the

effects of dc bias, temperature, and tolerances on the behavior

of the capacitors be evaluated for each application.

The peak-to-peak output voltage ripple for the selected output

capacitor and inductor values is calculated using the following

equation:

(

)

OUT

RIPPLE

≈

Capacitors with lower effective series resistance (ESR) are

preferable to guarantee low output voltage ripple, as shown in

the following equation:

RIPPLE

COUT

ESR

≤

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