ADP5065ACBZ-1-R7 datasheet(34/40 Pages) AD

34 / 40 page

ADP5065

Data Sheet

Rev. D | Page 34 of 40

PCB LAYOUT GUIDELINES

Poor layout can affect ADP5065 performance, causing electro-

magnetic interference (EMI) and electromagnetic compatibility

(EMC) problems, ground bounce, and voltage losses. Poor

layout can also affect regulation and stability. A good layout is

implemented using the following guidelines:



Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry

high switching frequencies, and large tracks act as antennas.



Route the output voltage path away from both the inductor

and SWxnode to minimize noise and magnetic interference.



Maximize the size of ground metal on the component side

to help with thermal dissipation.



Use a ground plane with several vias connecting to the

component side ground to further reduce noise

interference on sensitive circuit nodes.

CFILT

SW1

SW2

ISO_S1

ISO_S2

ISO_B1

ISO_B2

VDDIO

IIN_EXT

TRK_EXT

V_WEAK_SET

THR

TO MCU

TO MCU/NC

R3/NC

(OPTIONAL)

ADP5065

VIN = 4.5V TO 5.5V

10kΩ

CONNECT

CLOSE TO

BATTERY

L1 1µH

LQH32PN1R0NN0

VIN1

VIN2

BAT_SNS

SYS_ON_OK

CONTROL

(INPUT CURRENT,

DC-DC)

CHARGE CONTROL

(CHARGE MODE,

BATTERY ISOLATION)

SCL

SDA

VDDIO

TO MCU

1.5kΩ

Figure 40. Reference Circuit Diagram

PGND

11.5mm

VIN

ADP5065

CCFILT 4.7µF

CISO_B 22µF

Figure 41. PCB Layout Suggestion

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