PCF85363ATLSLASHA datasheet(24/86 Pages) NXP

24 / 86 page

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I2C-bus

aaa-009585

countdown value, WDR

WatchDog clock

counter

WDF

INTA or INTB

duration of WatchDog period after start

may range from WDR to WDR -1 counts

Figure 14. WatchDog single shot mode

7.5.1.3 WatchDog interrupts

The generation of interrupts from the WatchDog functions is controlled via the WatchDog

interrupt enable bits; WDIEA and WDIEB. These bits are in registers INTA_enable

(address 29h) and INTB_enable (address 2Ah).

The assertion of the flag WDF can be used to generate an interrupt at pins INTA and

INTB. The interrupt may be generated as a pulsed signal every time the WatchDog

counter reaches the end of the countdown period. Alternatively as a permanently

active signal which follows the condition of bit WDF. WDF remains set until cleared by

command.

When enabled, interrupts are triggered every time the WatchDog counter reaches the

end of the countdown period and even if the WDF is not cleared, an interrupt pulse can

be generated.

See Section 7.9 for interrupt control.

7.6 Single RAM byte

Bit

Symbol

Value

Description

7 to 0

B[7:0]

0000 0000[1] to

1111 1111

single RAM byte content

Table 18. RAM_byte - 8-bit RAM register (address 2Ch) bit description

[1]

Default value.

The PCF85363A provides a free single RAM byte, which can be used for any purpose,

for example, status bits of the system.

7.7 Timestamps

There are three timestamp registers which can be independently configured to record the

time for battery switch-over events and/or transitions on the TS pin.

Each timestamp register has an associated flag. It is also possible to generate an

interrupt signal for every timestamp register update.

PCF85363A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.1 — 18 June 2021

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