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PCF85363ATL/A 数据表(PDF) 9 Page - NXP Semiconductors |
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PCF85363ATL/A 数据表(HTML) 9 Page - NXP Semiconductors |
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9 / 86 page  NXP Semiconductors PCF85363A Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input, and I2C-bus Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 61. Bit Address Register name 7 6 5 4 3 2 1 0 Reference 14h TSR1_hr_xx_00_xx TSR1_HR_XX_00_XX (0 to 99) 15h TSR1_hr_00_xx_xx TSR1_HR_00_XX_XX (0 to 99) 16h not used - - - - - - - - Stop-watch timestamp2 (TSR2) 17h TSR2_seconds - TSR2_SECONDS (0 to 59) 18h TSR2_minutes - TSR2_MINUTES (0 to 59) 19h TSR2_hr_xx_xx_00 TSR2_HR_XX_XX_00 (0 to 99) 1Ah TSR2_hr_xx_00_xx TSR2_HR_XX_00_XX (0 to 99) 1Bh TSR2_hr_00_xx_xx TSR2_HR_00_XX_XX (0 to 99) 1Ch not used - - - - - - - - Section 7.7 Stop-watch timestamp3 (TSR3) 1Dh TSR3_seconds - TSR3_SECONDS (0 to 59) 1Eh TSR3_minutes - TSR3_MINUTES (0 to 59) 1Fh TSR3_hr_xx_xx_00 TSR3_HR_XX_XX_00 (0 to 99) 20h TSR3_hr_xx_00_xx TSR3_HR_XX_00_XX (0 to 99) 21h TSR3_hr_00_xx_xx TSR3_HR_00_XX_XX (0 to 99) 22h not used - - - - - - - - Section 7.7 Stop-watch timestamp mode control 23h TSR_mode TSR3M[1:0] - TSR2M[2:0] TSR1M[1:0] Section 7.7 Table 5. Stop-watch mode time registers...continued 7.1.2 Control registers overview Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 61. Bit Address Register name 7 6 5 4 3 2 1 0 Reference Offset register 24h Offset OFFSET[7:0] Section 7.8 Control registers 25h Oscillator CLKIV OFFM 12_24 LOWJ OSCD[1:0] CL[1:0] Section 7.10 26h Battery_switch - - - BSOFF BSRR BSM[1:0] BSTH Section 7.11 27h Pin_IO CLKPM TSPULL TSL TSIM TSPM[1:0] INTAPM[1:0] Section 7.12 28h Function 100TH PI[1:0] RTCM STOPM COF[2:0] Section 7.13 29h INTA_enable ILPA PIEA OIEA A1IEA A2IEA TSRIEA BSIEA WDIEA Section 7.9 2Ah INTB_enable ILPB PIEB OIEB A1IEB A2IEB TSRIEB BSIEB WDIEB Section 7.9 2Bh Flags PIF A2F A1F WDF BSF TSR3F TSR2F TSR1F Section 7.14 Single RAM byte 2Ch RAM_byte B[7:0] Section 7.6 WatchDog registers 2Dh WatchDog WDM WDR[4:0] WDS[1:0] Section 7.5 Stop 2Eh Stop_enable - - - - - - - STOP Section 7.16 Reset 2Fh Resets CPR 0 1 0 SR 1 0 CTS Section 7.15 RAM (64 byte) 40h to 7Fh RAM B[7:0] Section 7.17 Table 6. Control and function registers overview PCF85363A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 3.1 — 18 June 2021 9 / 86 |
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