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PCF85363ATL/A 数据表(PDF) 57 Page - NXP Semiconductors |
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PCF85363ATL/A 数据表(HTML) 57 Page - NXP Semiconductors |
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57 / 86 page  NXP Semiconductors PCF85363A Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input, and I2C-bus • address counter will roll over to address 00h • set time to 000000:00:00.00 • end I2C access 7.17 64 byte RAM In addition to the single RAM byte, there is a 64 byte RAM available from address 40h to 7Fh. The RAM can be written and read when the device is powered from VDD. The RAM content is backed-up when the device is powered from VBAT, but cannot be accessed as the interface is disabled. The address pointer is set during interface initiation and will auto increment after each byte access. The pointer will wrap around from address 7Fh to 40h after the last byte is accessed, (see Figure 5). 8 I2C-bus interface The I2C-bus is for bidirectional, two-line communication between different ICs. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. Both data and clock lines remain HIGH when the bus is not busy. The PCF85363A acts as a slave receiver when being written to and as a slave transmitter when being read from. Remark: When on VBAT power, the interface is not accessible. aaa-010487 Write ACK from slave S A A A P slave address + 0 write data write data write data A S A A A P read data read data read data A Read ACK from slave ACK from slave ACK from master slave address + 1 ACK from slave ACK from slave ACK from master ACK from slave Figure 32. I2C read and write protocol PCF85363A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 3.1 — 18 June 2021 57 / 86 |
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