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PCF85363ATL/A 数据表(PDF) 50 Page - NXP Semiconductors |
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PCF85363ATL/A 数据表(HTML) 50 Page - NXP Semiconductors |
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50 / 86 page ![]() NXP Semiconductors PCF85363A Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input, and I2C-bus [1] Default value. The STOP register bit in the Oscillator register (Section 7.10) is used to stop the counting of time in both RTC mode and stop-watch mode. Stopping of the oscillator can also be controlled from the TS pin. The TS pin must first be configured as an input by the TSPM[1:0] bits, then selected for active HIGH or active LOW by the TSL bits. STOP bit[1] TSL TS pin[2] Oscillator state Description 0 running 0 1 stopped TS pin active HIGH 0 stopped 0 1 1 running TS pin active LOW 1 - - stopped TS pin ignored Table 56. Oscillator stop control when STOPM = 1 [1] In the Oscillator register (Section 7.10). [2] TSPM[1:0] = 11. 7.13.5 COF[2:0]: Clock output frequency Frequency selection (Hz) Bit Symbol Value CLK pin TS pin INTA pin 000[1] 32 768 32 768 32 768 001 16 384 16 384 16 384 010 8 192 8 192 8 192 011 4 096 4 096 4 096 100 2 048 2 048 2 048 101 1 024 1 024 1 024 110 1 1 1 2 to 0 COF[2:0] 111 static LOW static LOW Hi-Z Table 57. COF[2:0] bits - Function control register (address 28h) [1] Default value. A programmable square wave is available at pin CLK. Operation is controlled by the COF[2:0] bits. Frequencies of 32.768 kHz (default) down to 1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. Pin CLK is a push-pull output and enabled at power-on. Pin CLK can be disabled by setting CLKPM = 1 in the Pin_IO register (Section 7.12). When disabled, the CLK pin is LOW. The selected clock frequency may also be output on the TS pin and the INTA pin. The CLKIV bit may be used to invert the clock output. CLKIV does not invert for the setting COF[2:0] = 111. The duty cycle of the selected clock is not controlled. However, due to the nature of the clock generation, all clock frequencies except 32.768 kHz have a duty cycle of 50 : 50. PCF85363A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 3.1 — 18 June 2021 50 / 86 |
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