PCF85363ATLSLASHA datasheet(62/86 Pages) NXP

62 / 86 page

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I2C-bus

• At t3, SW1 closes. The TS pin is now shorted to VSS. The TS pin has not been sampled

yet, so no action is taken by the IC.

• At t4, SW1 is closed. The internal pull-up resistor is enabled, but TS pin remains LOW.

The pin is then sampled and the LOW level detected. As the TSL bit was set for active

LOW detection, the HIGH-LOW transition of TS pin sampled triggers an event.

STOPM mode was configured to allow the TS pin to stop the time counting. As the TSL

bit was set for active LOW, time counting stops when the TS pin is LOW.

Timestamp register 2 was configured to take a copy of the time on an event of the TS

pin, hence TSR2 loads the time t4. TSR2F is also set.

INTA was configured to generate an interrupt when TSR2 loads a new time, hence an

interrupt pulse is seen on INTA.

• At t5, SW1 is opened. No action is taken by the IC.

• At t6, SW1 is open. The internal pull-up is active and the TS pin raises to vdd_int level.

The HIGH level is sampled and causes the stop signal to be released and time starts

counting again.

11 Internal circuitry

aaa-011071

PCF85363A

VDD

CLK

OSCI

VSS

OSCO

SCL

SDA

VBAT

INTA

Figure 36. Device diode protection diagram of PCF85363A

12 Safety notes

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe

precautions for handling electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5,

JESD625-A or equivalent standards.

PCF85363A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.1 — 18 June 2021

62 / 86

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