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ES9219C 数据表(PDF) 34 Page - ESS Technology,Inc

部件名 ES9219C
功能描述  32-bit Stereo Low Power DAC with Headphone Amplifier, Analog Volume Control, and Output Switch
PDF  67 Pages
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制造商  ESS [ESS Technology,Inc]
网页  http://www.esstech.com
标志 ESS - ESS Technology,Inc

ES9219C 数据表(HTML) 34 Page - ESS Technology,Inc

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ES9219 Datasheet
February 27, 2020
CONFIDENTIAL ADVANCE INFORMATION 1.0.4
ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801
34
0x87
135
ANALOG
CONTROL
OVERRIDES &
CMP/ATR
CONTROL
DISABLE_E
NCMP
DISABLE
_ATR_C
H2
DISABLE_AT
R_CH1
ENCMP_ALWA
YS_ON
SEL_PSD_1V
2
ENCMP
PDB_ATR_R
PDB_ATR_L
0x88
136
DRE CONFIG
DRE_FORC
E2
DRE_FO
RCE1
DRE_ENABL
E_PEAK_FILT
ER
DRE_VOLUME
_CTRL
DRE_ATR_DI
SABLE
RESERVED
RESERVED
ENABLE_DRE
0x89-
0x8A
137-138
DRE GAIN CH1
DRE_GAIN1
0x8B-
0x8C
139-140
DRE GAIN CH2
DRE_GAIN2
0x8D-
0x90
141-144
DRE ON
THRESHOLD
DRE_ON_THRESH
0x91
145
DRE DECAY RATE
RESERVED
DRE_DECAY_RATE
0x92
146
MQA CONFIG
MQA_ENAB
LE
RESERVED
0x93
147-151
RESERVED
RESERVED
0xC0
192
SOFT_RESET
RESERVED
AO_SOFT_RE
SET
0xC1
193
PLL CONFIG1
PLL_CP_PD
B
PLL_VCO
_PDB
RESERVED
PLL_VCO_BIAS_SEL
0xC2
194
PLL CONFIG2
PLL_CLK_FB_DIV[19:0]
0xC3
195
PLL CONFIG2
PLL_CLK_FB_DIV[19:0]
0xC4
196
PLL CONFIG2
PLL_CLK_IN_DIV[8:0]
PLL_CLK_FB_DIV[19:0]
0xC5
197
PLL CONFIG2
PLL_BYPAS
S
PLL_LO
W_BW
RESERVED
PLL_CLK_IN_DIV[8:0]
0xC6
198
PLL CONFIG3
PLL_CLK_OUT_DIV[8:0]
0xC7
199
PLL CONFIG3
PLL_PFD_DELAY_SEL
RESERVED
PLL_CP_BIAS_SEL
PLL_CLK_OUT
_DIV[8:0]
0xC8
200
PLL CONFIG4
RESERVED
PLL_HV_REG
_BYPASS
PLL_LV_REG_
BYPASS
PLL_HV_REG
_PDB
PLL_LV_REG
_PDB
PLL_VREF_SEL
0xC9
201
PLL CONFIG5
RESERVED
SEL_DAC_CLK
IN
PD_XTAL
PLL_INPUT_CLK
Table 1. Register Map



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