ES9219C datasheet(55/67 Pages) ESS

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ES9219 Datasheet

CONFIDENTIAL ADVANCE INFORMATION 1.0.4

February 27, 2020

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801

I2C Slave Access:

I2S Sync Slave Access:

Clock Domain:

Bits

[7:6]

[5]

[4]

[3]

[2]

[1]

[0]

Mnemo

nic

RESERV

DVDD_SHUNT_

ENB

RESERV

CH2_ANALOG_S

WAP

CH1_ANALOG_S

WAP

ENABLE_BCK_DET

ECT

ENABLE_WS_DET

ECT

Bits

Mnemonic

Description

[7:6]

RESERVED

[5]

DVDD_SHUNT_ENB

Enables the output shunt of the internal DVDD regulator.

1’b0: Shunt disabled

1’b1: Enable output shunt

[4]

RESERVED

[3]

CH2_ANALOG_SWAP

1’b0: Normal polarity of DAC2 and DAC2B (default).

1’b1: Swaps DAC2 and DAC2B (180 degree phase shift).

[2]

CH1_ANALOG_SWAP

1’b0: Normal polarity of DAC1 and DAC1B (default).

1’b1: Swaps DAC1 and DAC1B (180 degree phase shift).

[1]

ENABLE_BCK_DETECT

1’b0: Disable BCK monitor (default).

1’b1: Enable BCK monitor (assume normal MCLK exists). If BCK is lost (no pulses after 1024 MCLK

clock cycles), set LOCK_STATUS to 0 until normal BCK resumes.

[0]

ENABLE_WS_DETECT

1’b0: Disable WS monitor (default).

1’b1: Enable WS monitor (assume normal BCK exists). If WS is lost (no pulses after 256 BCK clock

cycles), set LOCK_STATUS to 0 until normal WS resumes.

I2C Slave Access:

I2S Sync Slave Access:

Clock Domain:

Bits

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Mnemonic

RESERV

DISABLE_ATR_CH

RESERVE

SEL_PSD_1V

ENCM

PDB_ATR_

Bits

Mnemonic

Description

[7]

RESERVED

[6]

DISABLE_ATR_CH2

1’b0: Ch2 Analog THD removal (ATR) is enabled (default).

1’b1: Ch2 Analog THD removal (ATR) is disabled.

[5]

DISABLE_ATR_CH1

1’b0: Ch1 Analog THD removal (ATR) is enabled (default).

1’b1: Ch1 Analog THD removal (ATR) is disabled.

[4]

RESERVED

[3]

SEL_PSD_1V2

Over current protection setting.

1’b0: set HPA output stage supply to 1.8V (default)

1’b1: set HPA output stage supply to 3.3V

[2]

ENCMP

Jack detection comparator enable

1’b0: Power down the comparator. (default)

1’b1: Comparator is enabled.

[1]

PDB_ATR_R

Analog THD Removal (ATR) power down control in the HPA for right channel.

1’b0: Power down the ATR. (default)

1’b1: ATR is enabled.

[0]

PDB_ATR_L

Analog THD Removal (ATR) power down control in the HPA for left channel.

1’b0: Power down the ATR. (default)

1’b1: ATR is enabled.

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