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ES9219C 数据表(PDF) 49 Page - ESS Technology,Inc |
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ES9219C 数据表(HTML) 49 Page - ESS Technology,Inc |
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49 / 67 page  ES9219 Datasheet CONFIDENTIAL ADVANCE INFORMATION 1.0.4 February 27, 2020 49 ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801 Bits [7] [6] [5:4] [3] [2] [1:0] Mnemonic RESERVED ENHPA_OUT RESERVED HPA_HIQ ENABLE_SEPARATE_THD_COMP RESERVED Bits Mnemonic Description [7] RESERVED NC [6] ENHPA_OUT Enable the headphone amplifier output stage, active high. 1’b0: Disable the headphone output stage (default). 1’b1: Enable the headphone output stage. Note: To reduce clicks/pops during power sequencing ENHPA_OUT should be delayed at least 100us after issuing the ENHPA signal. [5:4] RESERVED NA [3] HPA_HIQ Selects the quiescent current of the headphone amp. This may be useful for adjusting the crossover distortion between the left and right channel. 1’b0: Low output quiescent current (default). 1’b1: High output quiescent current. [2] ENABLE_SEPARATE_THD_COMP Selects which bank of THD coefficients to use for channel 2 compensation. 1’b0: One set of coefficients (registers 22-25) are used for both channel 1 and channel 2 (default). 1’b1: A separate set of coefficients (registers 53-56) are used for channel 2. [1:0] RESERVED NA Register 49-51: AUTOMATIC CLOCK GEARING THRESHOLDS I2C Slave Access: I2S Sync Slave Access: Clock Domain: Bits [23:12] [11:0] Mnemonic CLK_GEAR_MAX_THRESH CLK_GEAR_MIN_THRESH Bits Mnemonic Description [23:12] CLK_GEAR_MAX_THRESH Selects the maximum number of MCLK/2 pulses per 1fs that must be counted before the clock gear is automatically increased (MCLK is slowed down). [11:0] CLK_GEAR_MIN_THRESH Selects the minimum number of MCLK/2 pulses per 1fs that must be counted before the clock gear is automatically decreased (MCLK is sped up). This value should always be 98 or larger so that the minimum MCLK oversampling factor is achieved. Register 52: RESERVED Register 53-54: THD COMPENSATION C2 -CH2 I2C Slave Access: I2S Sync Slave Access: Clock Domain: Bits [15:0] Mnemonic THD_COMP_C2_Ch2 Bits Mnemonic Description [15:0] THD_COMP_C2_Ch2 A 16-bit signed coefficient for correcting for the second harmonic distortion. Used only in the channel 2 THD compensation block when enable_seperate_thd_comp is selected. |
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