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ES9219C 数据表(PDF) 61 Page - ESS Technology,Inc |
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ES9219C 数据表(HTML) 61 Page - ESS Technology,Inc |
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61 / 67 page ![]() ES9219 Datasheet CONFIDENTIAL ADVANCE INFORMATION 1.0.4 February 27, 2020 61 ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801 Register 200: PLL CONFIG4 I2C Slave Access: I2S Sync Slave Access: Clock Domain: Bits [7:6] [5] [4] [3] [2] [1:0] Mnemonic RESERVED PLL_HV_REG_BYPAS S PLL_LV_REG_BYPAS S PLL_HV_REG_PD B PLL_LV_REG_PD B PLL_VREF_SE L Bits Mnemonic Description [7:6] RESERVED NA [5] PLL_HV_REG_BYPASS High Voltage PLL Regulators Bypass. 1’b0: Normal operating mode (default). 1’b1: HV regulator in bypass mode; the output of HV regulator = AVDD [4] PLL_LV_REG_BYPASS Low Voltage PLL Regulator Bypass 1’b0: Normal operating mode (default). 1’b1: LV regulator in bypass mode; the output of LV regulator = DVCC [3] PLL_HV_REG_PDB High Voltage PLL regulator power down. 1’b0: PLL HV regulator is powered down. Output is shunted to ground (default). 1’b1: Normal operating mode [2] PLL_LV_REG_PDB Low Voltage PLL regulator power down 1’b0: PLL LV regulator is powered down. Output is shunted to ground (default). 1’b1: Normal operating mode [1:0] PLL_VREF_SEL PLL HV regulator output voltage select. 2’b00: 2V (default) 2’b01: 1.9V 2’b10: 1.8V 2’b11: 1.7V Register 201: PLL CONFIG5 I2C Slave Access: I2S Sync Slave Access: Clock Domain: Bits [7:5] [4] [3] [2:0] Mnemonic RESERVED SEL_DAC_CLKIN PD_XTAL PLL_INPUT_CLK Bits Mnemonic Description [7:5] RESERVED NA [4] SEL_DAC_CLKIN Select which clock is used for the DAC 1’b0: XTAL is selected as the DAC clock (default). 1’b1: PLL clock is selected as the DAC clock. [3] PD_XTAL XTAL circuit power down 1’b0: Normal operating mode (default). 1’b1: XTAL circuit is powered down. [2:0] PLL_INPUT_CLK Selects the input clock to the PLL 3’b:000 No clock is selected 3’b:001 MCLK is selected as PLL input clock 3’b:010 BCK is selected as PLL input clock 3’b:100 XTAL is selected as PLL input clock All other values are invalid, not allowed See System Clock XI/MCLK & BCK for more information |
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