ES9219C datasheet(47/67 Pages) ESS

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ES9219 Datasheet

CONFIDENTIAL ADVANCE INFORMATION 1.0.4

February 27, 2020

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801

I2C Slave Access:

I2S Sync Slave Access:

Clock Domain:

Bits

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Mnemonic

ENAUX

AREG_PDB

ENHPA

CPH_ENS

CPH_ENW

APDB

CP_CLKIO_SEL

RESERVED

Bits

Mnemonic

Description

[7]

ENAUX

Sets the state of the output switch when the digital core has taken control of the switch.

The switch can be controlled by the digital by setting ENAUX_OE to 1’b1.

1’b0: The switch is disengaged, allowing the DAC and headphone amplifier to drive the output (default).

1’b1: The switch is engaged, allowing the auxiliary input to drive the output.

Note: The switch should not be engaged when the headphone amplifier is enabled.

[6]

AREG_PDB

Enables the analog regulator, which uses the reference voltage enabled by the apdb signal.

1’b0: The analog regulator is disabled (default).

1’b1: The analog regulator is enabled. Note: apdb must be set to 1’b1 for the analog regulator to work correctly.

[5]

ENHPA

Enables the pre-amplifier for the headphone amplifier.

1’b0: The pre-amplifier is disabled (default).

1’b1: The pre-amplifier is enabled.

[4]

CPH_ENS

Enables the main charge pump and places it into strong mode. The main charge pump powers the output stage of

the headphone amplifier.

1’b0: The main charge pump (strong mode) is disabled (default).

1’b1: The main charge pump (strong mode) is enabled.

Note: encp_oe must be set to 1’b1 for the digital core to control the charge pump.

[3]

CPH_ENW

Enables the main charge pump and places it into weak mode. The main charge pump powers the output stage of

the headphone amplifier.

1’b0: The main charge pump is disabled (default).

1’b1: The main charge pump is enabled.

Note: encp_oe must be set to 1’b1 for the digital core to control the charge pump.

[2]

APDB

Enables the analog reference voltage, which is derived by a bandgap.

1’b0: The analog reference is disabled (default).

1’b1: The analog reference is enabled, which supplies a reference voltage for the analog regulator. This bit must

be set prior to enabling the analog regulator (AREG_PDB).

[1]

CP_CLK_SEL_IO

Disables the internal oscillator for the charge pump and uses a digitally generated clock signal instead. The

digitally generated clock signal can be configured via register 30-31.

1’b0: Use the internal oscillator as the charge pump clock (default).

1’b1: Use the digitally generated clock as the charge pump clock.

[0]

RESERVED

I2C Slave Access:

I2S Sync Slave Access:

Clock Domain:

Bits

[7]

[6:3]

[2]

[1]

[0]

Mnemonic

DIG_OVER_EN

RESERVED

SEL1V

SHTOUTb

SHTINb

Bits

Mnemonic

Description

[7]

DIG_OVER_EN

Allows the digital core to override the amp_mode settings via the contents of register 45, 46 and 47.

1’b0: Uses the amp_mode setting to control the analog sections (default).

1’b1: Allows the digital core to override the amp_mode settings.

[6:3]

RESERVED

[2]

SEL1V

Drops the digital power supply to 1V, which allows the supply to be driven externally.

1’b0: Use the internal digital power supply regulator (default).

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