ES9219C datasheet(60/67 Pages) ESS

60 / 67 page

ES9219 Datasheet

February 27, 2020

CONFIDENTIAL ADVANCE INFORMATION 1.0.4

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801

I2C Slave Access:

I2S Sync Slave Access:

Clock Domain:

Bits

[31]

[30]

[29]

[28:20]

[19:0]

Mnemonic

PLL_BYPASS

PLL_LOW_BW

RESERVED

PLL_CLK_IN_DIV[8:0]

PLL_CLK_FB_DIV[19:0]

Bits

Mnemonic

Description

[31]

PLL_BYPASS

PLL bypass mode

[30]

PLL_LOW_BW

PLL low bandwidth mode

[29]

RESERVED

[28:20]

PLL_CLK_IN_DIV[8:0]

Sets the PLL clock input divider:

9’d0: Reserved

9’d1: Divide by 1

9’d2: Divide by 2

9’dn: Divide by n

[19:0]

PLL_CLK_FB_DIV[19:0]

Sets the PLL clock feedback divider:

20’d0: Reserved

20’dn: Divide by 2^21/n

I2C Slave Access:

I2S Sync Slave Access:

Clock Domain:

Bits

[15:14]

[13:12]

[11:9]

[8:0]

Mnemonic

PLL_PFD_DELAY_SEL

RESERVED

PLL_CP_BIAS_SEL

PLL_CLK_OUT_DIV[8:0]

Bits

Mnemonic

Description

[15:14]

PLL_PFD_DELAY_SEL

Indicates the PFD minimum pulse.

2’b00: 8.5ns (default)

2’b01: 5.5ns

2’b10: 3.5ns

2’b11: 1.5ns

[13:12]

RESERVED

[11:9]

PLL_CP_BIAS_SEL

Sets the PLL charge pump bias current.

3’b000: 1uA (default)

3’b001: 2uA

3’b010: 3uA

3’b011: 4uA

3’b111: 8uA

[8:0]

PLL_CLK_OUT_DIV[8:0]

Indicates the PLL clock output divider.

9’d0: Reserved

9’dn: Divide by n

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