EM62100AGH datasheet(20/60 Pages) EMC

20 / 60 page

EM62100

65 COM/132 SEG STN LCD Driver

14 •

•••

Product Specification (V1.1) 09.13.2005

(This specification is subject to change without further notice)

6.3 Busy Flag

The busy flag is output to pin D7 by a read status command. When the busy flag is “1”

it indicates that the EM62100 chip is executing its internal operations, any command

other than status read is ignored during this time. If the cycle time (tCYC) is correct, this

flag need not be checked before each instruction. This makes vast improvements in

MPU processing capabilities possible.

6.4 Display Data RAM

The display data RAM stores the pixel data for the LCD. It is a 65

×132 addressable

array. It allows access to the desired bit by specifying the page address and the

column address. The 65 rows are divided into 8 pages of 8 lines and the 9th page with

a single line (D0). The D7 to D0 display data from the MPU corresponds to the LCD

common lines as show in Fig.4. There are few constraints at the time of display data

transfer when multiple EM62100 chip is used. However, the display structures can be

created easily and with a high degree of freedom. Reading from and writing to the

display RAM from the MPU side is performed through the I/O buffer, which is an

independent operation from signal reading for the liquid crystal driver. Consequently,

even if the display data RAM is accessed asynchronously, it will not cause adverse

effects on the display (such as flickering).

0 0 0

COM0

COM1

COM2

COM3

COM4

Display Data RAM

Liquid Crystal Display

Fig. 4

6.5 Page Address Circuit

The page address of the display data RAM is specified through the Page Address Set

Command. The page address needs to be specified again in accessing other pages.

Page address 8 is the page for the RAM region used only by the static indicators, and

only display data D0 is used.

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