EM62100AGH datasheet(31/60 Pages) EMC

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EM62100

65 COM/132 SEG STN LCD Driver

Product Specification (V1.1) 09.13.2005

•••• 25

(This specification is subject to change without further notice)

6.13 Reset Circuit

6.13.1 Initial Value of the Command Register

When the RESB input falls to “L”, the EM62100 will re-enter into its default state and the

following conditions occur.

1. Display OFF

2. Normal display

3. ADC select: Normal display (ADC command D0 = “L”)

4. Power control register (D2, D1, D0) = (0, 0, 0,)

5. The serial interface register data is reset to its initial value.

6. LCD power supply bias ratio: 1/9 (1/65 duty), 1/8 (1/49 duty), 1/6 (1/33 duty)

7. Read modify write: OFF

8. Static indicator: OFF

Static indicator register: (D1, D2) = (0, 0)

9. The Display start line register is set at the first line.

10. The Column address counter is set at address 0.

11. The Page address register is set at page 0.

12. Common output status: normal

13. The V0 voltage regulator internal power supply ratio is reset to its default value.

V0 voltage regulator internal resistor ratio register: (D2, D1, D0) = (1, 0, 0)

14. The Electronic volume register is reset to its default value.

Electronic volume register: (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0,)

15. Resets during Test mode

16. Oscillation frequency: 31.4kHz

17. Normal display mode and frame inversion status (partial display and N-Line

inversion release)

18. Partial display duty register: (D2, D1, D0) = (1, 0, 0), 1/65 duty

19. Partial display bias register: (D2, D1, D0) = (1, 0, 1), 1/9 bias

20. N-Line inversion register: (D4, D3, D2, D1, D0) = (0, 1, 1, 0, 0), 13-Line inversion

21. Partial start line register: (D5, D4, D3, D2, D1, D0) = (0, 0, 0, 0, 0, 0), the first line

22. DC/DC clock division register: (D3, D2, D1, D0) = (0, 0, 1, 1), fOSC/6

23. Output condition of COM, SEG

COM: VSS

SEG: VSS

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