UCS2113 datasheet(18/62 Pages) MICROCHIP

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UCS2113

DS20005680B-page 18

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5.1

UCS2113 Power States

Power states are indicators of the device’s current

consumption in the system and the functionality of the

digital logic. Table 5-1 details the UCS2113 power

states.

Table 5-2 shows the settings for the various power

states, except Off and Error. If VDD < VDD_TH, the

UCS2113 is in the Off state.

5.1.1

OFF STATE OPERATION

The device will be in the Off state if VDD is less than

VDD_TH. When the UCS2113 is in the Off state, it will do

nothing and all circuitry will be disabled. Digital register

values are not stored and the device will not respond to

SMBus commands.

5.1.2

SLEEP STATE OPERATION

The PWR_EN1 and PWR_EN2 pins may be used to

cause the UCS2113 to enter/exit Sleep. These pins are

AND’ed for Sleep mode.

When the UCS2113 is in the Sleep state, the device will

be in its lowest power state. The port power switch will

be disabled. VBUS1 and VBUS2 will be near ground

potential. The ALERT#1 and ALERT#2 pins will not be

asserted. If asserted prior to entering the Sleep state,

the ALERT# pin will be released. SMBus activity is lim-

ited to single byte read or write.

The first data byte read from the UCS2113 when it is in

the Sleep state will wake it; however, the data to be

read will return all 0’s and should be considered invalid.

This is a “dummy” read byte meant to wake the

UCS2113. Subsequent read or write bytes will be

accepted normally. After the dummy read, the

UCS2113 will be in a higher power state (see

Figure 5-2). After communication has not occurred for

tIDLE_SLEEP, the UCS2113 will return to Sleep.

TABLE 5-1:

POWER STATES DESCRIPTION

State

Description

Off

This power state is entered when the voltage at the VDD pin voltage is < VDD_TH. In this state, the device is

considered “off”. The UCS2113 will not retain its digital states and register contents nor respond to SMBus/I2C

communications. The port power switch will be off. See Section 5.1.1 “Off State Operation”.

Sleep

This is the lowest power state available. While in this state, the UCS2113 will retain digital functionality and wake

to respond to SMBus/I2C communications. See Section 5.1.2 “Sleep State Operation”.

Error

This power state is entered when a fault condition exists. Error power state is one or both channels in Fault

Handling. This state is updated as Priority One. The Interrupt Status Registers for each channel will update the

fault detected per channel. Only the channel that has detected a Fault will be affected since the other channel

can remain active if no fault is detected. See Section 5.1.4 “Error State Operation”.

Active

Active power State is one, or both channels active and sourcing current to the VBUS Port. This state is updated

as Priority Two. None of the channels have detected Fault. This power state provides full functionality. While in

this state, operations include activation of the port power switch, current limiting, and charge rationing. See

Section 5.1.3 “Active State Operation”.

TABLE 5-2:

POWER STATES CONTROL SETTINGS

Power

State

PWR_EN1 PWR_EN2

Behavior

Sleep

disabled

• All switches disabled

•VBUS will be near ground potential

• The UCS2113 wakes to respond to SMBus

communications

Active

enabled

disabled

• Port power switch is on for VBUS1

•VBUS2 pins are near ground potential or floating (Note 1)

disabled

enabled

• Port power switch is on for VBUS2

•VBUS1 pins are near ground potential or floating (Note 1)

enabled

• Port power switch is on for VBUS1 and VBUS2

Note 1: If the bit EN_VBUS_DISCHG is '1', the VBUS is discharged automatically and VBUS is near ground

potential. If the bit EN_VBUS_DISCHG is '0' then the corresponding VBUS pins are floating (VBUS

discharge is controlled by the SMBus host).

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