UCS2113 datasheet(25/62 Pages) MICROCHIP

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DS20005680B-page 25

UCS2113

6.3

Thermal Protection

The UCS2113 utilizes two-stage internal thermal

management. The first is triggered when the die

temperature exceeds TTSD_LOW threshold and the

second is triggered when the die temperature exceeds

TTSD_HIGH threshold.

6.3.0.1

THE FIRST THERMAL

SHUTDOWN STAGE (TTSD_LOW)

The first stage turns off the individual power switch

channel when the die temperature exceeds TTSD_LOW

threshold and a power switch operates in constant

current mode. It also causes the corresponding

channel to enter in error state and the corresponding

ALERT# pin will be asserted.

When an over-current condition appears, the power

switch operates in constant current mode for the

duration of tMASK time. Because of the increased

voltage drop across the switch, the die temperature

increases. If the die temperature exceeds TTSD_LOW

threshold before the expiration of the tMASK time, then

the power switch will open immediately.

If the TTSD_LOW threshold has been exceeded, but the

die temperature has not decreased below the

TTSD_LOW recovery threshold, then the power switch

cannot be closed when commanded by the PWR_EN1

or PWR_EN2 controls in the following situations:

• PWR_EN1 and/or PWR_EN2 controls transition

from inactive to active.

• it is a power up situation and PWR_EN1 and/or

PWR_EN2 pins are active.

In these situations, the corresponding channel will

enter in error state and the corresponding ALERT# pin

will be asserted.

The first thermal shutdown stage allows the two ports

to work independently, by preventing the die

temperature to increase during over-current conditions

and to exceed the maximum allowable temperature

(TTSD_HIGH).

The error state will persist and the power switches can

not be closed until the temperature is below

TTSD_LOW -TTSD_LOW_HYST.

6.3.0.2

THE SECOND THERMAL

SHUTDOWN STAGE (TTSD_HIGH)

The second thermal protection stage turns off both

power switches when the die temperature exceeds

TTSD_HIGH threshold, regardless of whether the power

switch channels are in current limit. It also causes both

channels to enter in error state and both ALERT#1 and

ALERT#2 pins to be asserted.

The error state will persist and the power switches

cannot be closed until the temperature is below

TTSD_HIGH - TTSD_HIGH_HYST.

6.4

VBUS Discharge

When the EN_VBUS_DISCHG bit from General

Configuration 2 Register is set (by default it is not set),

the UCS2113 will discharge VBUS through an internal

100

 resistor when at least one of the following

conditions occur:

• The PWR_EN control is disabled (triggered on the

inactive edge of the PWR_EN control).

• The VS voltage drops below a specified threshold

(VS_UVLO) that causes the port power switch to be

disabled.

• When commanded into the Sleep power state.

• Upon recovery from the Error state.

• When commanded via the SMBus in the Active

state.

When the automatic VBUS discharge circuitry is

activated, the UCS2113 will confirm that VBUS was

discharged at the end of the tDISCHARGE time. If the

VBUS voltage is not below the VTEST level, a discharge

error will be flagged (by setting the DISCH_ERR(1/2)

status bit) and the UCS2113 will enter the Error state.

When the EN_VBUS_DISCHG bit from General

Configuration 2 Register is not set (default setting), the

automatic VBUS discharges described above are

disabled. In this case, the SMBus host must set and

clear bits DISCHG_LOAD1 and DISCHG_LOAD2 from

the Current Limit Behavior Registers, to discharge the

VBUS1 and VBUS2. Setting the DISCHG_LOAD1 and

DISCHG_LOAD2 bits connects the internal 100



resistor to discharge the corresponding VBUS path.

This functionality doesn't use any timers. The

discharge time is controlled by the SMBus host, which

must clear this bit when its internal timer expires.

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