UCS2113 datasheet(20/62 Pages) MICROCHIP

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UCS2113

DS20005680B-page 20

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5.3

Supply Voltages

5.3.1

VDD SUPPLY VOLTAGE

The UCS2113 requires 4.5V to 5.5V to be present on

the VDD pin for core device functionality. Core device

functionality consists of maintaining register states and

wake-up upon SMBus/I2C query.

5.3.2

BACK-VOLTAGE DETECTION

The back-voltage detector is functional in all power

states (Sleep and Active).

When in Sleep, the UCS2113 will enter the Error state

from Sleep if a back-voltage condition was detected.

Whenever the following condition is true for either port,

the port power switch will be disabled and a

back-voltage event will be flagged. This will cause the

UCS2113 to enter the Error power state (see

Section 5.1.4 “Error State Operation”).

5.3.3

BACK-DRIVE CURRENT

PROTECTION

If a portable device is attached that is self-powered, it

may drive the VBUS port to its power supply voltage

level; however, the UCS2113 is designed such that

leakage current from the VBUS pins to the VDD and/or

the VS pin shall not exceed ILKG_1 (if the VDD and/or VS

voltage is zero) or ILKG_2 (if the VDD and/or VS voltage

exceeds VDD_TH and the power switch is open).

5.3.4

UNDERVOLTAGE LOCKOUT ON VS

The UCS2113 requires a minimum voltage (VS_UVLO)

be present on the VS pin for Active power state.

5.3.5

OVERVOLTAGE DETECTION AND

LOCKOUT ON VS

Both power switches will be disabled if the voltage on

any VS pin exceeds a voltage (VS_OV) for longer than

the specified time (tMASK). This will cause the device to

enter the Error state and both ALERT#1 and ALERT#2

pins will be asserted.

5.3.6

PWR_EN1 AND PWR_EN2 INPUT

The PWR_EN control affects the power state and enables

the port power switch to be turned on if conditions are met

(see Table 5-2). The port power switch cannot be closed

if PWR_EN is disabled. However, if PWR_EN is enabled,

the port power switch is not necessarily closed (see

Section 5.1.3 “Active State Operation”). In SMBus

mode, the PWR_EN1 and PWR_EN2 pins states will be

ignored by the UCS2113 if the PIN_IGN configuration bit

is set; otherwise, the PWR_EN1S and PWR_EN2S

configuration bits are checked along with the pins.

22 k



Active-High

2.13

2.13 + 2.13

SMBUS

27 k



Active-High

2.67

2.67 + 2.67

SMBUS

33 k



Active-High

3.2

3.2 + 3.2

SMBUS

47 k



Active-Low

0.53

0.53 + 0.53

Stand-Alone

56 k



Active-Low

0.96

0.96 + 0.96

Stand-Alone

68 k



Active-Low

1.07

1.07 + 1.07

Stand-Alone

82 k



Active-Low

1.28

1.28 + 1.28

Stand-Alone

100 k



Active-Low

1.6

1.6 + 1.6

Stand-Alone

120 k



Active-Low

2.13

2.13 + 2.13

Stand-Alone

150 k



Active-Low

2.67

2.67 + 2.67

Stand-Alone

VDD

Active-Low

3.2

3.2 + 3.2

Stand-Alone

Note 1: The total maximum current depends on power dissipation characteristics of the design (see Table 1-1).

TABLE 5-3:

COMMUNICATION DECODE (CONTINUED)

COMM_ILIM Pull Down

Resistor (±1%)

PWR_EN1 and

PWR_EN2 Polarity

ILIM (A)

Total ILIM (A)

(Note 1)

Communication

Mode

Note:

The VBUS voltage exceeds the VS and/or

the VDD pin voltage by VBV_TH and the

port power switch is closed. The port

power switch will be opened immediately.

If the condition lasts for longer than tMASK,

then the UCS2113 will enter the Error

state. Otherwise, the port power switch

will be turned on as soon as the condition

is removed.

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