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STM8S103F2 数据表(PDF) 75 Page - STMicroelectronics |
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STM8S103F2 数据表(HTML) 75 Page - STMicroelectronics |
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75 / 121 page  DocID15441 Rev 14 75/121 STM8S103F2 STM8S103F3 STM8S103K3 Electrical characteristics 88 10.3.7 Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Figure 35. Typical NRST VIL and VIH vs VDD @ 4 temperatures Table 42. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL(NRST) NRST input low level voltage(1) 1. Guaranteed by characterization results. --0.3 - 0.3 x VDD V VIH(NRST) NRST input high level voltage(1) IOL= 2 mA 0.7 x VDD - VDD+ 0.3 VOL(NRST) NRST output low level voltage(1) IOL= 3 mA - - 0.5 RPU(NRST) NRST pull-up resistor(2) 2. The RPU pull-up equivalent resistor is based on a resistive transistor. -30 55 80 k Ω tIFP(NRST) NRST input filtered pulse(3) -- - 75 ns tINFP(NRST) NRST Input not filtered pulse(3) 3. Guaranteed by design. -500 - - tOP(NRST) NRST output pulse(3) -20 - - µs |
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