STM8S103F2 datasheet(25/121 Pages) STMICROELECTRONICS

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STM8S103F2 STM8S103F3 STM8S103K3

Pinout and pin description

PC7/

SPI_MISO

I/O

Port C7

SPI master in/

slave out

PD0/

TIM1_BKIN

[CLK_CCO]

I/O

Port D0

Timer 1 -

break input

Configurabl

e clock

output

[AFR5]

PD1/

SWIM(4)

I/O

Port D1

SWIM data

interface

PD2

[TIM2_CH3]

I/O

Port D2

Timer 2 -

channel

3[AFR1]

128

PD3/

TIM2_CH2/

ADC_ETR

I/O

Port D3

Timer 2 -

channel

2/ADC

external

trigger

229

PD4/BEEP/

TIM2_CH1

I/O

Port D4

Timer 2 -

channel

1/BEEP

output

330

PD5/

UART1_TX

I/O

Port D5

UART1 data

transmit

431

PD6/

UART1_RX

I/O

Port D6

UART1 data

receive

532

PD7/ TLI

[TIM1_CH4]

I/O

Port D7

Top level

interrupt

Timer 1 -

channel 4

[AFR6]

1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the

total driven current must respect the absolute maximum ratings (see Section 10: Electrical characteristics).

2. When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for

waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode

if Halt/Active-halt is used in the application.

3. In the open-drain output column, “T” defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are

not implemented).

4. The PD1 pin is in input pull-up during the reset phase and after internal reset release.

Table 5. STM8S103K3 pin descriptions (continued)

Pin name

Input

Output

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