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STM8S103F2 数据表(PDF) 76 Page - STMicroelectronics |
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STM8S103F2 数据表(HTML) 76 Page - STMicroelectronics |
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76 / 121 page  Electrical characteristics STM8S103F2 STM8S103F3 STM8S103K3 76/121 DocID15441 Rev 14 Figure 36. Typical NRST pull-up resistance RPU vs VDD @ 4 temperatures Figure 37. Typical NRST pull-up current Ipu vs VDD @ 4 temperatures The reset network shown in Figure 38 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below VIL(NRST) max (see Table 42: NRST pin characteristics), otherwise the reset is not taken into account internally. For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry, attention must be taken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. Minimum recommended capacity is 100 nF. |
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