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STM8S103F2 数据表(PDF) 35 Page - STMicroelectronics |
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STM8S103F2 数据表(HTML) 35 Page - STMicroelectronics |
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35 / 121 page  DocID15441 Rev 14 35/121 STM8S103F2 STM8S103F3 STM8S103K3 Memory and register map 49 0x00 5208 to 0x00 520F Reserved area (8 byte) 0x00 5210 I2C I2C_CR1 I2C control register 1 0x00 0x00 5211 I2C_CR2 I2C control register 2 0x00 0x00 5212 I2C_FREQR I2C frequency register 0x00 0x00 5213 I2C_OARL I2C Own address register low 0x00 0x00 5214 I2C_OARH I2C Own address register high 0x00 0x00 5215 Reserved 0x00 5216 I2C_DR I2C data register 0x00 0x00 5217 I2C_SR1 I2C status register 1 0x00 0x00 5218 I2C_SR2 I2C status register 2 0x00 0x00 5219 I2C_SR3 I2C status register 3 0x0X 0x00 521A I2C_ITR I2C interrupt control register 0x00 0x00 521B I2C_CCRL I2C Clock control register low 0x00 0x00 521C I2C_CCRH I2C Clock control register high 0x00 0x00 521D I2C_TRISER I2C TRISE register 0x02 0x00 521E I2C_PECR I2C packet error checking register 0x00 0x00 521F to 0x00 522F Reserved area (17 byte) 0x00 5230 UART1 UART1_SR UART1 status register 0xC0 0x00 5231 UART1_DR UART1 data register 0xXX 0x00 5232 UART1_BRR1 UART1 baud rate register 1 0x00 0x00 5233 UART1_BRR2 UART1 baud rate register 2 0x00 0x00 5234 UART1_CR1 UART1 control register 1 0x00 0x00 5235 UART1_CR2 UART1 control register 2 0x00 0x00 5236 UART1_CR3 UART1 control register 3 0x00 0x00 5237 UART1_CR4 UART1 control register 4 0x00 0x00 5238 UART1_CR5 UART1 control register 5 0x00 0x00 5239 UART1_GTR UART1 guard time register 0x00 0x00 523A UART1_PSCR UART1 prescaler register 0x00 0x00 523B to 0x00 523F Reserved area (21 byte) Table 8. General hardware register map (continued) Address Block Register label Register name Reset status |
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