Data Sheet

ADE1202

Rev. 0 | Page 37 of 42

INTERRUPT MASK REGISTER

Address: 0x00B, Reset: 0x4000, Name: MASK

If a bit in the MASK register is set, the associated status flag generates an interrupt, with the exception of Bit 15, DREADY, as described in

Table 29.

Table 29. Bit Descriptions for MASK

Bits

Bit Name

Description

Reset

Access

15

DREADY

ADC Waveform Sample Interrupt Enable. Set this bit to 1 to enable 100 kHz interrupts

synchronized when ADC samples are ready. When this bit is enabled, all other interrupts must be

disabled with MASK register, Bits[14:0] equal to zero.

0x0

R/W

14

RSTDONE

Indicates that the device has reset and is ready to be programmed or begin default normal operation.

0x1

R/W

13

BUSY

Internal Communications Busy.

0x0

R/W

12

COOLDOWN2

Channel 2 Cool Down Mode Interrupt Enable. Set this bit to 1 to get an indication when channel

2 is in cool down mode to keep the device within a safe operating mode as configured by the

internal FET power meter.

0x0

R/W

11

COOLDOWN1

Channel 1 Cool Down Mode Interrupt Enable. Set this bit to 1 to get an indication when channel

1 is in cool down mode to keep the device within a safe operating mode as configured by the

internal FET power meter.

0x0

R/W

10

TSD

Programmable Load Thermal Shutdown Interrupt Enable. Set this bit to 1 to get an indication

when the programmable load has been disabled due to thermal protection.

0x0

R/W

9

COMFLT

Isolated Communication Error Interrupt Enable. Set this bit to 1 to get an indication when there

is an error in the internal data communicated between the isolated and nonisolated sides of the

device. The device deals with retransmitting packets. If this error persists after writing a 1 to the

COMFLT bit in the INT_STATUS register, then reconfigure the register settings in the device.

0x0

R/W

8

MEMFLT

Memory Fault Interrupt Enable. Set this bit to 1 to get an indication when there is a mismatch

between the register values on the isolated and nonisolated sides of the device, indicating the

registers must be reconfigured.

0x0

R/W

7

WARNC2

WARNC2 Interrupt Enable. Set this bit to 1 to get an indication when the WARNCx comparator

output goes from logic low to logic high for the Channel 2 input.

0x0

R/W

6

WARNB2

WARNB2 Interrupt Enable. Set this bit to 1 to get an indication when the WARNBx comparator

output goes from logic low to logic high for the Channel 2 input.

0x0

R/W

5

WARNA2

WARNA2 Interrupt Enable. Set this bit to 1 to get an indication when the WARNAx comparator

output goes from logic low to logic high for the Channel 2 input.

0x0

R/W

4

DOUT2

DOUT2 Interrupt Enable. Set this bit to 1 to get an indication when the DOUT2 output pin goes

from logic low to logic high.

0x0

R/W

3

WARNC1

WARNC1 Interrupt Enable. Set this bit to 1 to get an indication when the WARNCx comparator

output goes from logic low to logic high.

0x0

R/W

2

WARNB1

WARNB1 Interrupt Enable. Set this bit to 1 to get an indication when the WARNBx comparator

output goes from logic low to logic high.

0x0

R/W

1

WARNA1

WARNA1 Interrupt Enable. Set this bit to 1 to get an indication when the WARNAx comparator

output goes from logic low to logic high.

0x0

R/W

0

DOUT1

DOUT1 Interrupt Enable. Set this bit to 1 to get an indication when the DOUT1 pin changes from

logic low to logic high.

0x0

R/W

INTERRUPT STATUS REGISTER

Address: 0x00C, Reset: 0x0000, Name: INT_STATUS

The interrupt status register indicates which events capable of generating an interrupt have occurred. Write a 1 to the desired bit position

to acknowledge the event and then clear the bit. This register can be written while the device is locked.

Table 30. Bit Descriptions for INT_STATUS

Bits

Bit Name

Description

Reset

Access

15

RESERVED

Reserved.

0x0

R

14

RSTDONE

Indicates that the device has reset and is ready to be programmed or begin default normal

operation.

0x0

RW1C

13

BUSY

Internal Communications Busy.

0x0

RW1C

12

COOLDOWN2

Channel 2 is in cool down mode.

0x0

RW1C