Data Sheet

ADE1202

Rev. 0 | Page 11 of 42

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES

1. NC = NO CONNECT. THIS PIN IS INTERNALLY PULLED DOWN TO GNDF.

IT IS RECOMMENDED TO TIE THIS PIN TO GNDF EXTERNALLY.

1 2 3456 7 89 10

11

12

13

14

15

16

17

18

19

20

ADE1202

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration

Table 13. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

GNDF

The GNDF pin located at Pin 1 is used to provide a return path for current from the internal programmable load.

Both Pin 1 and Pin 10 must be connected to ground externally. See the Layout Guidelines section for

recommendations on how to connect this pin.

2

GATE

Use this pin to drive the gate pins of two enhancement mode field effect transistors (FETs), one for each channel of

the ADE1202.

3, 4

LOAD1,

LOAD2

Programmable Loads. Use these pins to command a preset current required for loading the relay contacts.

5, 6

IN1, IN2

Digital Input Pins. The scaled input signals are applied at these pins.

7

VDDL

1.8 V Output of the Analog Low Dropout (LDO) Regulator. Do not connect external load circuitry to this pin.

Decouple this pin to GNDF with the recommended capacitors shown in Table 16, and see the Layout Guidelines

section for recommendations on how to connect this pin.

8

NC

No Connect. This pin is internally pulled down to GNDF. It is recommended to tie this pin to GNDF externally.

9

VDDI

Isolated Secondary Side Power Supply Output Pin. This pin provides access to the 2.0 V, on-chip isolated power

supply. Decouple this pin to GNDF with the recommended capacitors shown in Table 16, and see the Layout

Guidelines section for recommendations on how to connect this pin. Do not connect external load circuitry to this pin.

10

GNDF

The GNDF pin located at Pin 10 is used as a reference for the internal, isolated power supply and the LDO regulator.

Both Pin 1 and Pin 10 must be connected to ground externally. See the Layout Guidelines section for

recommendations on how to connect this pin.

11

GND

GND Pin. This pin is the system controller side ground pin.

12

VDD

Primary Supply Voltage. This pin provides the supply voltage for the ADE1202. Maintain the supply voltage at

3.3 V ± 10% for specified operation. Decouple this pin to the GND pin with the recommended capacitors shown in

Table 16, and see the Layout Guidelines section for recommendations on how to connect this pin.

13

VLDO

1.8 V Output of the LDO Regulator. Decouple this pin to the GND pin with the recommended capacitors shown in

Table 16, and see the Layout Guidelines section for recommendations on how to connect this pin. Do not connect

external load circuitry to this pin.

14

DOUT1

15

DOUT2/IRQ

10 kΩ pull-up resistor to the VDD voltage is recommended.

16

ADDR

Address Mode Pin. This pin is used for multichip addressing. If multichip addressing is not used, connect this pin to

ground. The address divider requires 1% resistors, as described in the SPI ADE1202 Addressing section.

17

CS

Chip Select for SPI Port.

18

SCLK

Serial Clock Input for SPI Port. All serial data transfers are synchronized to this clock.

19

MOSI

Data Input for SPI Port.

20

MISO

Data Output for SPI Port.