ADE1202 datasheet(18/42 Pages) AD

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ADE1202

Data Sheet

Rev. 0 | Page 18 of 42

Decimation

The data from the ADC is passed through a decimator. The

decimation filter averages N samples and then decimates by N,

where N is 2, 4, or 8, as configured in the DECRATE bits

(Bits[2:1]) in the BIN_CTRL register (see Table 15). The

decimation filter topology is shown in Figure 27. To enable the

decimation, set Bit 0 (DECIMATE) to 1 in the BIN_CTRL

the ADC bypasses the decimator.

Table 15. Decimation Settings

DECRATE Bit Setting

Number of Samples

Bypass the decimator

AVERAGED BY N

DECIMATED BY N

Figure 27. Decimation Filter Topology

Digital Datapaths

Four datapaths process the data coming out of the decimator,

including comparators and debounce filtering.

One datapath, DOUTx, is capable of driving the DOUTx

output, as shown in Figure 26. The output can also be read over

the SPI.

Three additional datapaths, WARNAx, WARNBx, and WARNCx

are provided for the user to configure warnings. The output of

the warning datapaths can be read over the SPI.

Both digital input channels, IN1 and IN2, share the same digital

datapath settings.

Set Bit 15 of the BIN_FILTER, WARNA_FILTER, WARNB_

FILTER, and WARNC_FILTER registers to enable the

comparator and debounce filters.

Comparator Function

Each comparator includes a high threshold level and a low

threshold level. The thresholds are programmable between 0x00

and 0xFF. An INx pin voltage of 1.25 V/PGA translates to 0xFF.

To calculate the threshold register value based on the desired

threshold voltage and input signal level, use the following

equation:

THR = (THRESHOLD/(1.25/PGA)) × 255

(1)

where:

THR is the value that is written in the BIN_THR, WARNA_THR,

WARNB_THR, and WARNC_THR control registers.

THRESHOLD is the desired threshold level expressed in V.

PGA is the PGA gain selected by the PGA_GAIN register.

The BIN_THR register contains the configuration used for the

DOUT1 and DOUT2 datapaths, which can be output on the

DOUT1 pin and DOUT2 pin.

The WARNA_THR, WARNB_THR, and WARNC_THR

registers contain the configuration for the warning channels.

Each comparator has four configurable modes: hysteretic mode,

midrange mode, greater than (GT) mode, and lesser than

(LT) mode. They are selected by the BIN_MODE, WARNA_

MODE, WARNB_MODE, and WARNC_MODE bits in the

BIN_CTRL register. After reset, the DOUT1 and DOUT2

channels are in hysteretic mode, the WARNAx channel is in

GT mode, the WARNBx channel is in midrange mode, and the

WARNCx channel is in LT mode.

Comparator in Hysteretic Output Mode

In hysteretic output mode, when the ADC output is greater

than the high threshold level of the comparator, the output is set

high. The output is set low when the ADC output drops below

the low threshold level. The behavior of the comparator in the

hysteretic output mode is shown in Figure 28.

TIME

HIGH THRESHOLD

LEVEL

LOW THRESHOLD

LEVEL

ADC

OUTPUT

COMPARATOR

OUTPUT

TIME

Figure 28. Comparator Behavior in Hysteretic Output Mode

Comparator in Midrange Output Mode

In midrange output mode, when the ADC output is less than

the high threshold level and greater than the low threshold level,

the comparator output is set high. The output is set low when

the ADC output drops below the low threshold level or goes

above the high threshold level. The behavior of the comparator

in the midrange output mode is shown in Figure 29.

TIME

HIGH THRESHOLD

LEVEL

LOW THRESHOLD

LEVEL

ADC

OUTPUT

COMPARATOR

OUTPUT

TIME

Figure 29. Comparator Behavior in Midrange Output Mode

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