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Data Sheet

ADE1202

Rev. 0 | Page 29 of 42

LAYOUT GUIDELINES

Figure 23 shows the schematic of the typical ADE1202

application circuit.

A 4-layer PCB is recommended for the application circuit.

Figure 48 shows the recommended layout to interface two

digital input channels given on P0 and P1 with one ADE1202.

Figure 48. ADE1202 Circuit Board, Top Layer

Figure 49 shows a close up of the Figure 48 layout, focusing on

the critical areas around the ADE1202.

Figure 49. Close Up of the ADE1202 Support Circuitry

FERRITE BEAD

A ferrite bead is placed on the drain of each FET to prevent

parasitics in the application circuit from resonating with the

FET at high frequencies (hundreds of MHz).

Place a ferrite bead near the drain of each FET (see the yellow

Circle 1 labels in Figure 49).

DECOUPLING AND GROUND PLANE CONNECTION

A low inductance path to the ground plane is required. It is

recommended to use multiple vias to lower the inductance and

provide multiple connections to the GNDF ground pins, Pin 1

and Pin 10.

When placing the decoupling capacitors, ensure that the smaller

capacitor, 0.1 µF, is placed as close as possible to the VDDI pin

and GNDF pin (Pin 10) to provide a low inductance from the

pin to the capacitor, and from the capacitor to ground.

Figure 50 and Figure 51 show close ups of the recommended

layout around the ADE1202 Pin 1 and Pin 10, which are

indicated by the yellow Circle 2 labels in Figure 49.

Figure 50. ADE1202 Pin 1 Close Up

Figure 51. ADE1202 Pin 10 Close Up

Similar rules apply for decoupling on the isolated side for the

GND and VDD supplies on Pin 11 and Pin 12 (see the yellow

Circle 4 label in Figure 49).

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