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ADE1202 数据表(PDF) 6 Page - Analog Devices

部件名 ADE1202
功能描述  Dual Channel, Configurable, Isolated Digital Input
PDF  42 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE1202 数据表(HTML) 6 Page - Analog Devices

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ADE1202
Data Sheet
Rev. 0 | Page 6 of 42
TIMING CHARACTERISTICS
Table 3. Input Signal Timing Characteristics
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Input Signal Filter Resolution1
20
μs
Time Delay from Step Change on INx Input to DOUTx
Change State
60
86
110
μs
BIN_FILTER_VAL = 3, with step on INx from 0 V to 0.8 V
Power-Up Time
110
ms
With initial VDDI = 0 V, using recommended circuit in
Figure 23
ADDR Pin Load Time1
320
μs
After power-on (see Figure 25)
1 Guaranteed by design.
Table 4. Programmable Load Switching Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
Turn On Rise Time
tR
2
9
μs
In high idle mode with a 50 mA pulse
Pulsed Current On Time
tPK
4
4.1
4.3
ms
HIGH_TIME = 400
Turn Off Fall Time
tF
0.025
μs
tR
tF
tPK
HIGH CURRENT
MAXIMUM
LOW CURRENT
MAXIMUM
0%
100%
PROGRAMMABLE LOAD
CURRENT
Figure 2. Programmable Load Switching Characteristics
Table 5. SPI Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
CS to SCLK Negative Edge
tSS
10
ns
SCLK Frequency1
fSCLK
0.00025
10
MHz
SCLK Low Pulse Width
tSL
40
ns
SCLK High Pulse Width
tSH
40
ns
Data Output Valid After SCLK Edge
tDAV
40
ns
Data Input Setup Time Before SCLK Edge
tDSU
10
ns
Data Input Hold Time After SCLK Edge
tDHD
10
ns
Data Output Fall Time
tDF
10
ns
Data Output Rise Time
tDR
10
ns
SCLK Rise Time
tSR
10
ns
SCLK Fall Time
tSF
10
ns
MISO Disable After CS Rising Edge
tDIS
100
ns
CS High After SCLK Edge
tSFS
0
ns
1 Guaranteed by design and characterization.



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