ADE1202 datasheet(16/42 Pages) AD

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ADE1202

Data Sheet

Rev. 0 | Page 16 of 42

THEORY OF OPERATION

The ADE1202 is a dual channel, configurable, isolated digital

input monitor designed for energy transmission and

distribution applications. The ADE1202 contains an isolated

and a nonisolated side (see Figure 24).

Only a single 3.3 V supply is required to power the ADE1202.

The isolated side (the VDDI pin and GNDF pin) is supplied

from an internal, isolated dc-to-dc converter, which is generated

from the VDD pin and GND pin on the nonisolated side. The

isoPower technology eliminates the need for an external,

isolated power supply.

The isolated side of the device contains a PGA, an SAR ADC, a

programmable load, and a gate drive.

Digital isolators allow the isolated side to communicate with the

nonisolated side.

The nonisolated side signal conditions the ADC data coming

from the isolated side and creates the DOUT1 and DOUT2

digital outputs. The digital outputs reflect the status of the IN1

and IN2 digital inputs from the isolated side.

The SPI is used to initialize the ADE1202 and can be used to

monitor status and ADC waveforms during operation.

POWER SUPPLY AND CONDITIONING

VDD, VLDO, and GND Pins

Connect the VDD pin to a 3.3 V logic level supply. Decouple

these pins to the GND pin with the recommended capacitors

shown in Table 16, and see the Layout Guidelines section for

recommendations on how to make these connections.

GNDF Pins

The GNDF pins are used to reference the high voltage side circuits

after the isolation barrier. The GNDF pin located at Pin 1 is used to

provide a return path for current from the internal programmable

load. The GNDF pin located at Pin 10 is used as a reference for

internal, isolated power supply and the LDO regulator. Both

Pin 1 and Pin 10 are required to be connected to the high voltage

ground plane on the PCB. The detailed grounding method is

described in the Layout Guidelines section.

VDDI and VDDL Supplies

The VDDI pin is the 2.0 V, isolated side power supply output,

and the VDDL pin is the 1.8 V output of the analog LDO

regulator. Decouple these pins to GNDF (Pin 10) with the

recommended capacitors shown in Table 16, and see the Layout

Guidelines section for recommendations.

Note that no external component can be supplied from the

VDDI and GNDF isolated power supply outputs.

Power-Up

At power-up, the following steps must be taken by the host

controller managing a system formed by one or multiple

ADE1202 devices:

Supply 3.3 V to the VDD pin. The dc-to-dc converter

powers up and supplies the isolated side of the ADE1202.

The full device becomes functional. See Table 3 for the

power-up time.

To determine when the ADE1202 devices are ready to

accept commands, read the INT_STATUS register of each

device until Bit 14 (RSTDONE) is set to 1.

Use the SPI to initialize the configuration registers

(BIN_FILTER, PL_EN, and PGA_GAIN) of each ADE1202.

Write 0xADE1 to the LOCK register to complete the

configuration process.

DECIMATION

COMPARATOR

FILTERING

OUTPUT CONTROL

SPI PORT

PROGRAMMABLE

LOAD

GATE DRIVE

LDO

REGULATOR

VDD

GND

VLDO

DOUT1

DOUT2/IRQ

ADDR

SCLK

MOSI

MISO

GNDF

VDDI

VDDL

GATE

LOAD1

GNDF

RECTIFIER

PGA

IN2

IN1

LOAD2

DATA

ISOLATION

POWER

ISOLATION

ISOLATED SIDE

NONISOLATED SIDE

ADC

LDO

REGULATOR

Figure 24. ADE1202 Nonisolated and Isolated Sides

ADE1202 数据表(PDF) 16 Page - Analog Devices

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