ADE1202 datasheet(17/42 Pages) AD

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Data Sheet

ADE1202

Rev. 0 | Page 17 of 42

ADE1202

POWERS UP

2.4V TO 2.6V

3.3V ± 10%

ADE1202

POWERED UP

150ms

320µs

ADE1202

POWER-ON RESET TIMER

TURNED ON

RSTDONE

INTERRUPT

TRIGGERED

ADE1202

READY

MICROPROCESSOR

ACCESSES

ADE1202 SPI

ADDRESS PIN

VALUE SAMPLED

SPI READS BACK AS 0xFFFF

Figure 25. Power-Up Procedure for ADE1202 System

PGA

SAR

ADC

DATA

ISOLATION

DECIMATION

COMPARATOR

DEBOUNCE

DOUTx PIN

WARNAx

WARNBx

WARNCx

INx

DOUTx

STATUS,

INT_STATUS

Figure 26. Digital Input Signal Path

DIGITAL INPUTS SIGNAL PATH

A typical ADE1202 application circuit is shown in Figure 23, which

includes external scaling using a voltage divider. The acceptable

input voltage between the INx and GNDF pins is given in Table 1.

Using the application circuit shown in Figure 23, ac input

signals are half wave rectified, as shown in Figure 23, and

require 10 ms + pickup time.

Figure 26 shows a detailed view of the digital signal conditioning

done within the ADE1202 IC to generate a DOUTx digital

output signal based on the input measured on the INx pins.

The following sections describe the functionality of each circuit

in detail.

PGA

The PGA stage allows four scaling factors, as shown in Table 14.

The input voltage range is the same as the INx input voltage

range (VIN in Table 1 and Table 14). To configure the gain over

the SPI, write to the PGA_GAIN register (Address 0x201),

Bits[1:0] (PGA_GAIN). It is recommended to choose the gain

that maximizes the range of the internal ADC, as shown in

Table 14, without setting the system thresholds outside the range of

the PGA.

By default, the PGA_GAIN bits are cleared to 00, which means

the PGA is set to 1.

Table 14. PGA Gain Settings

VIN

PGA

PGA_GAIN Register, Bits[1:0]

1.25

1×

0.625

2×

0.25

5×

0.125

10×

SAR ADC

After the PGA stage, the ADE1202 SAR ADC produces 8-bit

outputs, as shown in Figure 26. The ADE1202 has two

multiplexed channels that share one ADC. The ADC samples at

100 kSPS and each INx channels is sampled at 50 kSPS. The

digitized data is then passed through the isolation barrier.

To get an indication of when new ADC samples are ready,

configure the DOUT2/IRQ pin as an interrupt by setting the

IRQ_PIN_MODE bit in the CTRL register, and write 0x8000 to

the MASK register. The DOUT2/IRQ pin goes high for 1 μs and

then low for 9 μs at a rate of 100 kSPS, indicating when new

ADC samples are ready. When reading ADC samples, Bit 15 in

the MASK register, DREADY, must be the only interrupt

enabled so that MASK = 0x8000.

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