ADE1202

Data Sheet

Rev. 0 | Page 2 of 42

TABLE OF CONTENTS

Features .............................................................................................. 1

 

Applications....................................................................................... 1

 

General Description ......................................................................... 1

 

Product Highlights ........................................................................... 1

 

Revision History ............................................................................... 2

 

Functional Block Diagram .............................................................. 3

 

Specifications..................................................................................... 4

 

Electrical Characteristics............................................................. 4

 

Timing Characteristics ................................................................ 6

 

Insulation and Safety Related Specifications ............................ 7

 

Package Characteristics ............................................................... 7

 

Regulatory Information............................................................... 8

 

DIN V VDE V 0884-11 (VDE V 0884-11) Insulation

Characteristics .............................................................................. 9

 

Absolute Maximum Ratings.......................................................... 10

 

Thermal Resistance .................................................................... 10

 

ESD Caution................................................................................ 10

 

Pin Configuration and Function Descriptions........................... 11

 

Typical Performance Characteristics ........................................... 12

 

Test Circuit ...................................................................................... 15

 

Theory of Operation ...................................................................... 16

 

Power Supply and Conditioning .............................................. 16

 

Digital Inputs Signal Path.......................................................... 17

 

Invalid Mode ............................................................................... 20

 

Programmable Load Current.................................................... 20

 

External FET Protection............................................................ 22

 

Gate Drive.................................................................................... 23

 

Thermal Shutdown..................................................................... 24

 

Interrupt....................................................................................... 24

 

SPI Protocol Overview............................................................... 24

 

Protecting the Integrity of Configuration Registers .............. 27

 

Version ......................................................................................... 27

 

Insulation Wear Out................................................................... 27

 

Layout Guidelines........................................................................... 29

 

Ferrite Bead ................................................................................. 29

 

Decoupling and Ground Plane Connection........................... 29

 

Electomagnetic Interface (EMI) Capacitor............................. 30

 

Applications Information .............................................................. 31

 

Register Map ................................................................................... 32

 

Register Details ............................................................................... 33

 

Lock Register............................................................................... 33

 

Control Register ......................................................................... 33

 

Binary Channel Control Register............................................. 34

 

Binary Channel Threshold Level Register .............................. 35

 

WARNAx Channel Threshold Level Register ........................ 35

 

WARNBx Channel Threshold Level Register......................... 35

 

WARNCx Channel Threshold Level Register ........................ 35

 

Binary Channel Configuration Register ................................. 36

 

WARNAx Datapath Configuration Register .......................... 36

 

WARNBx Datapath Configuration Register........................... 36

 

WARNCx Datapath Configuration Register .......................... 36

 

Interrupt Mask Register............................................................. 37

 

Interrupt Status Register............................................................ 37

 

Status Register............................................................................. 38

 

ADC Register .............................................................................. 38

 

ADC Decimated Register.......................................................... 39

 

Programmable Load Control Register .................................... 39

 

Programmable Load Rise Threshold Register........................ 39

 

Programmable Load Low Code Register ................................ 39

 

Programmable Load High Code Register............................... 40

 

Programmable Load High Current Period Register.............. 40

 

Energy Meter Control Register ................................................ 40

 

Energy Meter Maximum Threshold Register......................... 40

 

Energy Meter Channel 1 Accumulator Register .................... 41

 

Energy Meter Channel 2 Accumulator Register .................... 41

 

Programmable Load Enable Register ...................................... 41

 

PGA Gain Register ..................................................................... 41

 

Outline Dimensions ....................................................................... 42

 

Ordering Guide .......................................................................... 42

 

REVISION HISTORY

12/2019—Revision 0: Initial Version