ADP1850ACPZ-R7 datasheet(25/32 Pages) AD

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Data Sheet

ADP1850

Rev. C | Page 25 of 32

PCB LAYOUT GUIDELINES

In any switching converter, there are some circuit paths that

carry high dI/dt, which can create spikes and noise. Some

circuit paths are sensitive to noise, while other circuits carry

high dc current and can produce significant IR voltage drops.

The key to proper PCB layout of a switching converter is to

identify these critical paths and arrange the components and

the copper area accordingly. When designing PCB layouts,

be sure to keep high current loops small. In addition, keep

compensation and feedback components away from the switch

nodes and their associated components.

The following is a list of recommended layout practices for the

synchronous buck controller, arranged by decreasing order of

importance.

MOSFETS, INPUT BULK CAPACITOR, AND BYPASS

CAPACITOR

The current waveform in the top and bottom FETs is a pulse

with very high dI/dt; therefore, the path to, through, and from

each individual FET should be as short as possible, and the two

paths should be commoned as much as possible. In designs that

use a pair of D-Pak, or a pair of SO-8 FETs, on one side of the

PCB, it is best to counter-rotate the two so that the switch node

is on one side of the pair. This allows the high-side FET’s drain

to be bypassed to the low-side FET’s source with a suitable

ceramic bypass capacitor placed as close as possible to the FETs.

Close proximity of the bypass capacitor minimizes the

inductance around the loop through the FETs and capacitor.

The recommended bypass ceramic capacitor values range from

1 µF to 22 µF, depending on the output current. The ceramic

bypass capacitor is usually connected to a larger value bulk filter

capacitor and should be grounded to the PGNDx plane.

HIGH CURRENT AND CURRENT SENSE PATHS

Part of the ADP1850 architecture is sensing the current across

the low-side FET between the SWx and PGNDx pins. The

switching GND currents of one channel creates noise and

can be picked up by the other channel. It is essential to have

Kelvin sensing connection between SWx and the drain of the

respective low-side MOSFET, and between PGNDx and the

source of the respective low-side MOSFET, as illustrated in

Figure 43. Place these Kelvin connections very close to the

FETs to achieve accurate current sensing. Figure 43 illustrates

the proper connection technique for the SW1/SW2, PGND1/

PGND2, and PGND plane.

ADP1850

DH1

SW1

VOUT1

VIN

PGND

PLANE

COUT1

CIN1

VOUT2

VIN

COUT2

CIN2

PGND2

DL2

SW2

DH2

DL1

PGND1

AGND

PLANE

KELVIN

CONNECTIONS

Figure 43. Grounding Technique for Two Channels

SIGNAL PATHS

The negative terminals of VIN bypass, compensation

components, soft start capacitor, and the bottom end of the

output feedback divider resistors should be tied to a small

AGND plane. These connections should attach from their

respective pins to the AGND plane and should be as short as

possible. No high current or high dI/dt signals should be

connected to this AGND plane. The AGND area should be

connected through one wide trace to the negative terminal of

the output filter capacitors.

PGND PLANE

The PGNDx pin handles a high dI/dt gate drive current returning

from the source of the low side MOSFET. The voltage at this pin

also establishes the 0 V reference for the overcurrent limit

protection function and the ILIMx pin. A PGND plane should

connect the PGNDx pin and the VDL bypass capacitor, 1 µF,

through a wide and direct path to the source of the low side

MOSFET. The placement of CIN is critical for controlling

ground bounce. The negative terminal of CIN must be placed

very close to the source of the low-side MOSFET.

FEEDBACK AND CURRENT-LIMIT SENSE PATHS

Avoid long traces or large copper areas at the FBx and ILIMx

pins, which are low-level signal inputs that are sensitive to

capacitive and inductive noise pickup. It is best to position

any series resistors and capacitors as close as possible to these

pins. Avoid running these traces close and/or parallel to high

dI/dt traces.

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