ADP1850ACPZ-R7 datasheet(19/32 Pages) AD

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Data Sheet

ADP1850

Rev. C | Page 19 of 32

OUTPUT CAPACITOR SELECTION

Choose the output bulk capacitor to set the desired output voltage

ripple. The impedance of the output capacitor at the switching

frequency multiplied by the ripple current gives the output

voltage ripple. The impedance is made up of the capacitive

impedance plus the nonideal parasitic characteristics, the

equivalent series resistance (ESR), and the equivalent series

inductance (ESL). The output voltage ripple can be

approximated by













∆

≅

∆

ESL

OUT

ESR

OUT

where:

∆V

OUT is the output ripple voltage.

∆I

L is the inductor ripple current.

RESR is the equivalent series resistance of the output capacitor (or

the parallel combination of ESR of all output capacitors).

LESL is the equivalent series inductance of the output capacitor

(or the parallel combination of ESL of all capacitors).

Solving COUT in the previous equation yields

ESL

ESR

OUT

∆

−

∆

−

∆

≅

Usually the capacitor impedance is dominated by ESR. The

maximum ESR rating of the capacitor, such as in electrolytic or

polymer capacitors, is provided in the manufacturer’s data

sheet; therefore, output ripple reduces to

ESR

OUT

∆

≅

∆

Electrolytic capacitors also have significant ESL, on the order of

5 nH to 20 nH, depending on type, size, and geometry. PCB

traces contribute some ESR and ESL, as well. However, using

the maximum ESR rating from the capacitor data sheet usually

provides some margin such that measuring the ESL is not

usually required.

In the case of output capacitors where the impedance of the

ESR and ESL are small at the switching frequency, for instance,

where the output capacitor is a bank of parallel MLCC capaci-

tors, the capacitive impedance dominates and the output

capacitance equation reduces to

OUT

∆

≅

Make sure that the ripple current rating of the output capacitors

is greater than the maximum inductor ripple current.

During a load step transient on the output, for instance, when

the load is suddenly increased, the output capacitor supplies the

load until the control loop has a chance to ramp the inductor

current. This initial output voltage deviation results in a voltage

droop or undershoot. The output capacitance, assuming 0 Ω

SR, required to satisfy the voltage droop requirement is

approximated by

DROOP

STEP

OUT

∆

≅

where:

∆ISTEP is the step load.

∆VDROOP is the voltage droop at the output.

When a load is suddenly removed from the output, the energy

stored in the inductor rushes into the capacitor, causing the

output to overshoot. The output capacitance required to satisfy

the output overshoot requirement can be approximated by

)

(

OUT

OVERSHOOT

OUT

STEP

OUT

−

∆

≅

where:

∆VOVERSHOOT is the overshoot voltage during the step load.

Select the largest output capacitance given by any of the

previous three equations.

MOSFET SELECTION

The choice of MOSFET directly affects the dc-to-dc converter

performance. A MOSFET with low on resistance reduces I2R

losses, and low gate charge reduces transition losses. The

MOSFET should have low thermal resistance to ensure that the

power dissipated in the MOSFET does not result in excessive

MOSFET die temperature.

The high-side MOSFET carries the load current during on time

and usually carries most of the transition losses of the converter.

Typically, the lower the on resistance of the MOSFET, the

higher the gate charge and vice versa. Therefore, it is important

to choose a high-side MOSFET that balances the two losses. The

conduction loss of the high-side MOSFET is determined by the

equation













≅

OUT

DSON

LOAD

)

(

where:

RDSON is the MOSFET on resistance.

The gate charging loss is approximated by the equation

≅

where:

VPV is the gate driver supply voltage.

QG is the MOSFET total gate charge.

Note that the gate charging power loss is not dissipated in the

MOSFET but rather in the ADP1850 internal drivers. This

power loss should be taken into consideration when calculating

the overall power efficiency.

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