ADP1850

Data Sheet

Rev. C | Page 8 of 32

Pin No.

Mnemonic

Description

15

ILIM2

Current Limit Sense Comparator Inverting Input for Channel 2. Connect a resistor between ILIM2 and SW2 to set

the current limit offset. For accurate current limit sensing, connect ILIM2 to a current sense resistor at the source

of the low-side MOSFET.

16

BST2

Boot-Strapped Upper Rail of High Side Internal Driver for Channel 2. Connect a multilayer ceramic capacitor

(0.1 µF to 0.22 µF) between BST2 and SW2. There is an internal boost rectifier connected between VDL and BST2.

17

SW2

Switch Node for Channel 2. Connect to source of the high-side N-channel MOSFET and the drain of the low-side

N-channel MOSFET of Channel 2.

18

DH2

High-Side Switch Gate Driver Output for Channel 2. Capable of driving MOSFETs with total input capacitance up

to 20 nF.

19

PGND2

Power Ground for Channel 2. Ground for internal Channel 2 driver. Differential current is sensed between SW2

and PGND2. Use the Kelvin sensing connection technique between PGND2 and source of the low-side MOSFET.

20

DL2

Low-Side Synchronous Rectifier Gate Driver Output for Channel 2. To set the gain of the current sense amplifier,

connect a resistor between DL2 and PGND2. Capable of driving MOSFETs with a total input capacitance up to 20 nF.

21

DL1

Low-Side Synchronous Rectifier Gate Driver Output for Channel 1. To set the gain of the current sense amplifier,

connect a resistor between DL1 and PGND1. Capable of driving MOSFETs with a total input capacitance up to 20 nF.

22

PGND1

Power Ground for Channel 1. Ground for internal Channel 1 driver. Differential current is sensed between SW1

and PGND1. Use the Kelvin sensing connection technique between PGND1 and source of the low-side MOSFET.

23

DH1

High-Side Switch Gate Driver Output for Channel 1. Capable of driving MOSFETs with a total input capacitance

up to 20 nF.

24

SW1

Power Switch Node for Channel 1. Connect to source of the high-side N-channel MOSFET and the drain of the

low-side N-channel MOSFET of Channel 1.

25

BST1

Boot-Strapped Upper Rail of High Side Internal Driver for Channel 1. Connect a multilayer ceramic capacitor

(0.1 µF to 0.22 µF) between BST1 and SW1. There is an internal boost diode or rectifier connected between VDL

and BST1.

26

ILIM1

Current Limit Sense Comparator Inverting Input for Channel 1. Connect a resistor between ILIM1 and SW1 to set

the current limit offset. For accurate current limit sensing, connect ILIM1 to a current sense resistor at the source

of the low-side MOSFET.

27

PGOOD1

Power Good. Open-drain power-good indicator logic output with an internal 12 kΩ resistor connected between

PGOOD1 and VCCO. PGOOD1 is pulled to ground when the Channel 1 output is outside the regulation window.

An external pull-up resistor is not required.

28

SS1

Soft Start Input for Channel 1. Connect a capacitor from SS1 to AGND to set the soft start period. This node is

internally pulled up to 5 V with a 6.5 µA current source.

29

RAMP1

Connect a resistor from RAMP1 to VIN to set up a ramp current for slope compensation in Channel 1. The voltage

at RAMP2 is 0.2 V. This pin is high impedance when the channel is disabled.

30

COMP1

Compensation Node for Channel 1. Output of Channel 1 error amplifier. Connect a series resistor-capacitor

network from COMP1 to AGND to compensate the regulation control loop.

31

FB1

Output Voltage Feedback for Channel 1. Connect to Output 1 via a resistor divider.

32

TRK1

Tracking Input for Channel 1. Connect TRK1 to VCCO if tracking is not used.

33

(EPAD)

Exposed Pad

(EPAD)

Connect the bottom exposed pad of the LFCSP package to the system AGND plane.