ADP1850ACPZ-R7 datasheet(14/32 Pages) AD

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ADP1850

Data Sheet

Rev. C | Page 14 of 32

SYNCHRONOUS RECTIFIER AND DEAD TIME

The synchronous rectifier (low-side MOSFET) improves efficiency

by replacing the Schottky diode that is normally used in an

asynchronous buck regulator. In the ADP1850, the antishoot-

through circuit monitors the SW and DL nodes and adjusts the

low-side and high-side drivers to ensure break-before-make

switching which prevents cross-conduction or shoot-through

between the high-side and low-side MOSFETs. This break-

before-make switching is known as dead time, which is not

fixed and depends on how fast the MOSFETs are turned on

and off. In a typical application circuit that uses medium sized

MOSFETs with input capacitance of approximately 3 nF, the

typical dead time is approximately 30 ns. When small and fast

MOSFETs with fast diode recovery time are used, the dead time

can be as low as 13 ns.

INPUT UNDERVOLTAGE LOCKOUT

When the bias input voltage, VIN, is less than the undervoltage

lockout (UVLO) threshold, the switch drivers stay inactive.

When VIN exceeds the UVLO threshold, the switchers start

switching.

INTERNAL LINEAR REGULATOR

The internal linear regulator is low dropout (LDO) meaning it

can regulate its output voltage, VCCO. VCCO powers up the

internal control circuitry and provides power for the gate

drivers. It is guaranteed to have more than 200 mA of output

current capability, which is sufficient to handle the gate drive

requirements of typical logic threshold MOSFETs driven at up

to 1.5 MHz. VCCO is always active and cannot be shut down by

the EN1 and EN2 pins. Bypass VCCO to AGND with a 1 µF or

greater capacitor.

Because the LDO supplies the gate drive current, the output of

VCCO is subject to sharp transient currents as the drivers

switch and the boost capacitors recharge during each switching

cycle. The LDO has been optimized to handle these transients

without overload faults. Due to the gate drive loading, using the

VCCO output for other external auxiliary system loads is not

recommended.

The LDO includes a current limit well above the expected

maximum gate drive load. This current limit also includes a

short-circuit fold back to further limit the VCCO current in the

event of a short-circuit fault.

The VDL pin provides power to the low-side driver. Connect

VDL to VCCO. Bypass VDL to PGNDx with a 1 µF (minimum)

ceramic capacitor, which must be placed close to the VDL pin.

For an input voltage less than 5.5 V, it is recommended to

bypass the LDO by connecting VIN to VCCO, as shown in

Figure 26, thus eliminating the dropout voltage. However, if

the input range is 4 V to 7 V, the LDO cannot be bypassed by

shorting VIN to VCCO because the 7 V input has exceeded the

maximum voltage rating of the VCCO pin. In this case, use the

LDO to drive the internal drivers, but keep in mind that there is

a dropout when VIN is less than 5 V.

VIN = 2.75V TO 5.5V

ADP1850

VIN

VCCO

Figure 26. Configuration for VIN < 5.5 V

OVERVOLTAGE PROTECTION

The ADP1850 has a built-in circuit for detecting output over-

voltage at the FB node. When the FB voltage, VFB, rises above

the overvoltage threshold, the low-side N-channel MOSFET

(NMOSFET) is immediately turned on, and the high-side

NMOSFET is turned off until the VFB drops below the

undervoltage threshold. This action is known as the crow-

bar overvoltage protection. If the overvoltage condition is

not removed, the controller maintains the feedback voltage

between the overvoltage and undervoltage thresholds, and the

output is regulated to within typically +8% and −8% of the

regulation voltage. During an overvoltage event, the SS node

discharges toward zero through an internal 3 kΩ pull-down

resistor. When the voltage at FBx drops below the undervoltage

threshold, the soft start sequence restarts. Figure 27 shows the

overvoltage protection scheme in action in PSM.

CH1 20.0V

CH2 5.00V

CH3 1.00V

CH4 10.0V

M100µs

A CH1

10.0V

DH1

PGOOD1

VO1 = 1.8V SHORTED TO 2V SOURCE

VIN

Figure 27. Overvoltage Protection in PSM

POWER GOOD

The PGOODx pin is an open-drain NMOSFET with an internal

12 kΩ pull-up resistor connected between PGOODx and VCCO.

PGOODx is internally pulled up to VCCO during normal

operation and is active low when tripped. When the feedback

voltage, VFB, rises above the overvoltage threshold or drops

below the undervoltage threshold, the PGOODx output is

pulled to ground after a delay of 12 µs. The overvoltage or

undervoltage condition must exist for more than 10 µs for

PGOODx to become active. The PGOODx output also

becomes active if a thermal overload condition is detected.

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