ADP1850ACPZ-R7 datasheet(24/32 Pages) AD

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ADP1850

Data Sheet

Rev. C | Page 24 of 32

Another ratiometric tracking configuration is having the slave

channel rise more quickly than the master channel, as shown in

Figure 40 and Figure 41. The tracking circuits in Figure 39 and

Figure 41 are virtually identical with the exception that RTRKB >

RTRKT as shown in Figure 41.

TIME

SLAVE VOLTAGE

MASTER VOLTAGE

Figure 40. Ratiometric Tracking (Slave Channel Has a Faster Ramp Rate)

ADP1850

EN2

EN1

FB2

FB1

TRK1

SS1

VCCO

TRK2

SS2

10kΩ

45.3kΩ

RTRKB

10kΩ

RTRKT

5kΩ

2.2V

3.3V

VOUT1_MASTER

CSS2

20nF

CSS1

100nF

RBOT

10kΩ

RTOP

20kΩ

1.8V

VOUT2_SLAVE

Figure 41. Example of a Ratiometric Tracking Circuit (Slave Channel Has a

Faster Ramp Rate)

INDEPDENDENT POWER STAGE INPUT VOLTAGE

In addition to the single power supply configuration, the power

stage input voltage of the dc-to-dc converter can come from a

different voltage supply, as illustrated in Figure 42. The range of

the power stage input voltage (VPIN) is 1 V to 20 V. For instance,

the bias input voltage (VIN) is 5 V, VPIN can be as low as 1 V or as

high as 20 V. The user needs to make sure that the minimum

or the maximum duty cycle is not violated in this operating

condition. Furthermore, note that RRAMP is connected to VPIN.

VIN = 2.7V TO 20V

VIN

ADP1850

DH1

FB1

DL1

PGND1

SW1

VOUT1

VPIN = 1V TO 20V

RAMP1

RRAMP1

DH2

RAMP2

FB2

DL2

PGND2

SW2

VOUT2

VPIN = 1V TO 20V

RRAMP2

Figure 42. Independent Power Stage Input Voltage (Simplified Schematic)

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