ADP1850ACPZ-R7 datasheet(22/32 Pages) AD

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ADP1850

Data Sheet

Rev. C | Page 22 of 32

CONFIGURATION AND LOOP COMPENSATION

(DUAL-PHASE OPERATION)

In dual-phase operation, the two outputs of the switching

regulators are shorted together and can source more than

50 A of output current depending on the selection of the

power components. Internal parameters in the ADP1850

are optimized and trimmed in the factory to minimize the

mismatch in output currents between the two channels. See

Figure 34 and Figure 47 for a configuration of a typical dual-

phase application circuit. Note that FB1 shorts to FB2, SS1 to

SS2, and COMP1 to COMP2, where the outputs of the two

error amplifiers are shared. Furthermore, the controller needs

to be placed in forced PWM operation by connecting SYNC

to VCCO or logic high.

The equations for calculating the loop compensation compo-

nents are identical to the single-phase operation, but the

combined value of Gm of the error amplifiers, the modulator

gain and the effective fSW are all doubled.

RAMP1

RRAMP1

VIN

DH1

BST1

SW1

ILIM1

FB1

DL1

PGND1

RAMP2

DH2

BST2

SW2

ILIM2

FB2

DL2

PGND2

EN1

EN2

VDL

VCCO

TRK1

TRK2

SYNC

FREQ

COMP1

COMP2

SS1

SS2

AGND

RCSG1

RCSG2

VOUTx

VIN

RRAMP2

PGOOD1

PGOOD2

ADP1850

Figure 34. Dual-Phase Circuit

SWITCHING NOISE AND OVERSHOOT REDUCTION

In any high speed step-down regulator, high frequency noise

(generally in the range of 50 MHz to 100 MHz) and voltage

overshoot are always present at the gate, the switch node (SW),

and the drains of the external MOSFETs. The high frequency

noise and overshoot are caused by the parasitic capacitance,

CGD, of the external MOSFET and the parasitic inductance of

the gate trace and the packages of the MOSFETs. When the high

current is switched, electromagnetic interference (EMI) is

generated, which can affect the operation of the surrounding

circuits. To reduce voltage ringing and noise, it is recommended

to add an RC snubber between SWx and PGNDx for high current

applications, as illustrated in Figure 35.

In most applications, RSNUB is typically 2 Ω to 4 Ω, and CSNUB

typically 1.2 nF to 3 nF.

RSNUB can be estimated by

OSS

MOSFET

SNUB

≅

And CSNUB can be estimated by

OSS

SNUB

≅

where:

LMOSFET is the total parasitic inductance of the high-side and

low-side MOSFETs, typically 3 nH, and is package dependent.

COSS is the total output capacitance of the high-side and low-

side MOSFETs given in the MOSFET data sheet.

The size of the RC snubber components needs to be chosen

correctly to handle the power dissipation. The power dissipated

in RSNUB is

SNUB

In most applications, a component size 0805 for RSNUB is sufficient.

However, the use of an RC snubber reduces the overall efficiency,

generally by an amount in the range of 0.1% to 0.5%. The RC

snubber does not reduce the voltage overshoot. A resistor,

shown as RRISE in Figure 35, at the BSTx pin helps to reduce

overshoot and is generally between 2 Ω and 4 Ω. Adding a

resistor in series, typically between 2 Ω and 4 Ω, with the gate

driver also helps to reduce overshoot. If a gate resistor is added,

then RRISE is not needed.

VIN

ADP1850

(CHANNEL 1)

DH1

VDL

DL1

ILIM1

RILIM1

SW1

BST1

PGND1

RRISE

VOUTx

CSNUB

COUT

RSNUB

Figure 35. Application Circuit with a Snubber

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