DVR datasheet(203/416 Pages) MICROCHIP

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DS30010118D-page 203

PIC24FJ256GA705 FAMILY

FIGURE 17-1:

SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)

17.3

Audio Mode Operation

To initialize the SPIx module for Audio mode, follow the

steps to initialize it for Master/Slave mode, but also set

the AUDEN bit (SPIxCON1H<15>). In Master+Audio

mode:

• This mode enables the device to generate SCKx

and LRC pulses as long as the SPIEN bit

(SPIxCON1L<15>) = 1.

• The SPIx module generates LRC and SCKx

continuously in all cases, regardless of the

transmit data, while in Master mode.

• The SPIx module drives the leading edge of LRC

and SCKx within 1 SCKx period, and the serial

data shifts in and out continuously, even when the

TX FIFO is empty.

In Slave+Audio mode:

• This mode enables the device to receive SCKx

and LRC pulses as long as the SPIEN bit

(SPIxCON1L<15>) = 1.

• The SPIx module drives zeros out of SDOx, but

does not shift data out or in (SDIx) until the

module receives the LRC (i.e., the edge that

precedes the left channel).

• Once the module receives the leading edge

of LRC, it starts receiving data if

DISSDI (SPIxCON1L<4>) = 0 and the serial data

shifts out continuously, even when the TX FIFO

is empty.

Read

Write

Internal

Data Bus

SDIx

SDOx

SSx/FSYNC

SCKx

MSB

Shift

Control

Edge

Select

Enable Master Clock

Transmit

Peripheral Clock

MCLKEN

SPIxRXSR

URDTEN

TXELM<5:0> = 6’b0

MSB

Baud Rate

Generator

SSx & FSYNC

Control

Clock

Control

SPIxTXSR

Clock

Control

Receive

SPIxURDT

SPIxTXB

Edge

Select

SPIxRXB

Note 1: The MCLK source is the REFO clock.

MCLK(1)

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